From 96597a70dcb978269930f193d6c7998e897b87ad Mon Sep 17 00:00:00 2001 From: Sid Manning Date: Wed, 10 Sep 2014 13:09:25 +0000 Subject: [PATCH] Add missing HWEncoding to base register class. This change gives tblgen the information needed to fill in the HexagonRegEncodingTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217500 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonRegisterInfo.td | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index 8ea1b7e75db..52f79a163dc 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -13,46 +13,48 @@ let Namespace = "Hexagon" in { - class HexagonReg : Register { + class HexagonReg num, string n> : Register { field bits<5> Num; + let HWEncoding{4-0} = num; } - class HexagonDoubleReg subregs> : + class HexagonDoubleReg num, string n, list subregs> : RegisterWithSubRegs { field bits<5> Num; + let HWEncoding{4-0} = num; } // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers. - class Ri num, string n> : HexagonReg { + class Ri num, string n> : HexagonReg { let Num = num; } // Rf - 32-bit floating-point registers. - class Rf num, string n> : HexagonReg { + class Rf num, string n> : HexagonReg { let Num = num; } // Rd - 64-bit registers. class Rd num, string n, list subregs> : - HexagonDoubleReg { + HexagonDoubleReg { let Num = num; let SubRegs = subregs; } // Rp - predicate registers - class Rp num, string n> : HexagonReg { + class Rp num, string n> : HexagonReg { let Num = num; } // Rc - control registers - class Rc num, string n> : HexagonReg { + class Rc num, string n> : HexagonReg { let Num = num; } // Rj - aliased integer registers - class Rj: HexagonReg { + class Rj: HexagonReg { let Num = R.Num; let Aliases = [R]; } -- 2.34.1