From 97c573d5de4f729f9b3a5db59c6daa3a6fc7efe4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 20 Nov 2008 02:25:51 +0000 Subject: [PATCH] Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59696 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMCodeEmitter.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index b621c41e12a..56fc55315f7 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -686,9 +686,7 @@ unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, const TargetInstrDesc &TID) const { - unsigned e = TID.getNumOperands(); - if (e) --e; // Looks at the last non-implicit operand as well. - for (unsigned i = MI.getNumOperands(); i != e; --i) { + for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ const MachineOperand &MO = MI.getOperand(i-1); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) return 1 << ARMII::S_BitShift; -- 2.34.1