From 981f1d9f9634e84fbb3f55e8547aba44cdf18ea9 Mon Sep 17 00:00:00 2001 From: chenxing Date: Tue, 9 Jul 2013 11:08:40 +0800 Subject: [PATCH] rk3188: Priority setting i2s under cpll to fix i2s frac div do not effect, let axi_cpu's pll different with i2s's --- arch/arm/mach-rk3188/clock_data.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c index 4d0f734e608b..10ddea3c72ea 100755 --- a/arch/arm/mach-rk3188/clock_data.c +++ b/arch/arm/mach-rk3188/clock_data.c @@ -3413,10 +3413,14 @@ void rk30_clock_common_i2s_init(void) i2s_rate = 49152000; } - if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) { - clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk); - } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) { + /* + * Priority setting i2s under cpll to fix i2s frac div do not effect, let + * axi_cpu's pll different with i2s's + * */ + if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) { clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk); + } else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) { + clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk); } else { if(general_pll_clk.rate > codec_pll_clk.rate) clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk); -- 2.34.1