From 98330ff8e344d2e88c0a2166901d394e813e8162 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Sat, 20 Mar 2010 06:05:13 +0000 Subject: [PATCH] Fix a very bad typo. Since the register number was off by one, the ARM load/store optimizer would incorrectly think that registers D26 and D28 were consecutive and would generate a VLDM instruction to load them. The assembler was not convinced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMBaseRegisterInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 11e1c4862b4..b380c954d60 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -80,7 +80,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, case D23: return 23; case D24: return 24; case D25: return 25; - case D26: return 27; + case D26: return 26; case D27: return 27; case D28: return 28; case D29: return 29; -- 2.34.1