From 98a393c499fe1f1043c2813facd9868bba5a0b01 Mon Sep 17 00:00:00 2001 From: David Wu Date: Thu, 22 Oct 2015 16:38:25 +0800 Subject: [PATCH] pwm: rockchip: add pwm supported for rk3228 Change-Id: I30d816d4bca2fb532b009505947d1465732a2f07 Signed-off-by: David Wu --- arch/arm/boot/dts/rk3228.dtsi | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi index cdee2e5221e5..7b8a842cd2b0 100644 --- a/arch/arm/boot/dts/rk3228.dtsi +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -381,6 +381,50 @@ compatible = "rockchip,screen"; }; + pwm0: pwm@110b0000 { + compatible = "rockchip,rk-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&clk_gates9 7>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&clk_gates9 7>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&clk_gates9 7>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + clocks = <&clk_gates9 7>; + clock-names = "pclk_pwm"; + status = "disabled"; + }; + vop: vop@20050000 { compatible = "rockchip,rk3228-lcdc"; -- 2.34.1