From 9a06cce0f2088a298f357b933fb7d8e268f6ca52 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 2 Feb 2006 06:43:15 +0000 Subject: [PATCH] Implement MaskedValueIsZero for ANY_EXTEND nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25900 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index c861762d16d..c79045b8859 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -154,6 +154,11 @@ bool TargetLowering::MaskedValueIsZero(const SDOperand &Op, case ISD::ZERO_EXTEND: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits))); + case ISD::ANY_EXTEND: + // If the mask only includes bits in the low part, recurse. + SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); + if (Mask >> SrcBits) return false; // Use of unknown top bits. + return MaskedValueIsZero(Op.getOperand(0), Mask); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. -- 2.34.1