From 9c0068f0a38597a5914b69a5e1b5a949027a5464 Mon Sep 17 00:00:00 2001 From: Wesley Peck Date: Mon, 20 Dec 2010 20:43:24 +0000 Subject: [PATCH] Teach the MBlaze asm parser how to parse special purpose register names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122261 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/MBlaze/MBlazeInstrInfo.td | 9 +- lib/Target/MBlaze/MBlazeRegisterInfo.cpp | 119 +++++++++++++++------ lib/Target/MBlaze/MBlazeRegisterInfo.h | 1 + lib/Target/MBlaze/MBlazeRegisterInfo.td | 43 +++++++- test/MC/MBlaze/mblaze_special.s | 128 ++++++++++++++++++++++- 5 files changed, 258 insertions(+), 42 deletions(-) diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.td b/lib/Target/MBlaze/MBlazeInstrInfo.td index 0979091ad91..186ede5febb 100644 --- a/lib/Target/MBlaze/MBlazeInstrInfo.td +++ b/lib/Target/MBlaze/MBlazeInstrInfo.td @@ -83,7 +83,6 @@ def brtarget : Operand; def calltarget : Operand; def simm16 : Operand; def uimm5 : Operand; -def uimm14 : Operand; def uimm15 : Operand; def fimm : Operand; @@ -600,11 +599,11 @@ let isCodeGenOnly=1 in { //===----------------------------------------------------------------------===// // Misc. instructions //===----------------------------------------------------------------------===// -def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg), - "mfs $dst, $rg", [], IIAlu>; +def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src), + "mfs $dst, $src", [], IIAlu>; -def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg), - "mts $dst, $rg", [], IIAlu>; +def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src), + "mts $dst, $src", [], IIAlu>; def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set), "msrset $dst, $set", [], IIAlu>; diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp index 45da9eadfef..2e1bd974bf1 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.cpp +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.cpp @@ -48,38 +48,62 @@ MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) /// MBlaze::R0, return the number that it corresponds to (e.g. 0). unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) { switch (RegEnum) { - case MBlaze::R0 : return 0; - case MBlaze::R1 : return 1; - case MBlaze::R2 : return 2; - case MBlaze::R3 : return 3; - case MBlaze::R4 : return 4; - case MBlaze::R5 : return 5; - case MBlaze::R6 : return 6; - case MBlaze::R7 : return 7; - case MBlaze::R8 : return 8; - case MBlaze::R9 : return 9; - case MBlaze::R10 : return 10; - case MBlaze::R11 : return 11; - case MBlaze::R12 : return 12; - case MBlaze::R13 : return 13; - case MBlaze::R14 : return 14; - case MBlaze::R15 : return 15; - case MBlaze::R16 : return 16; - case MBlaze::R17 : return 17; - case MBlaze::R18 : return 18; - case MBlaze::R19 : return 19; - case MBlaze::R20 : return 20; - case MBlaze::R21 : return 21; - case MBlaze::R22 : return 22; - case MBlaze::R23 : return 23; - case MBlaze::R24 : return 24; - case MBlaze::R25 : return 25; - case MBlaze::R26 : return 26; - case MBlaze::R27 : return 27; - case MBlaze::R28 : return 28; - case MBlaze::R29 : return 29; - case MBlaze::R30 : return 30; - case MBlaze::R31 : return 31; + case MBlaze::R0 : return 0; + case MBlaze::R1 : return 1; + case MBlaze::R2 : return 2; + case MBlaze::R3 : return 3; + case MBlaze::R4 : return 4; + case MBlaze::R5 : return 5; + case MBlaze::R6 : return 6; + case MBlaze::R7 : return 7; + case MBlaze::R8 : return 8; + case MBlaze::R9 : return 9; + case MBlaze::R10 : return 10; + case MBlaze::R11 : return 11; + case MBlaze::R12 : return 12; + case MBlaze::R13 : return 13; + case MBlaze::R14 : return 14; + case MBlaze::R15 : return 15; + case MBlaze::R16 : return 16; + case MBlaze::R17 : return 17; + case MBlaze::R18 : return 18; + case MBlaze::R19 : return 19; + case MBlaze::R20 : return 20; + case MBlaze::R21 : return 21; + case MBlaze::R22 : return 22; + case MBlaze::R23 : return 23; + case MBlaze::R24 : return 24; + case MBlaze::R25 : return 25; + case MBlaze::R26 : return 26; + case MBlaze::R27 : return 27; + case MBlaze::R28 : return 28; + case MBlaze::R29 : return 29; + case MBlaze::R30 : return 30; + case MBlaze::R31 : return 31; + case MBlaze::RPC : return 0x0000; + case MBlaze::RMSR : return 0x0001; + case MBlaze::REAR : return 0x0003; + case MBlaze::RESR : return 0x0005; + case MBlaze::RFSR : return 0x0007; + case MBlaze::RBTR : return 0x000B; + case MBlaze::REDR : return 0x000D; + case MBlaze::RPID : return 0x1000; + case MBlaze::RZPR : return 0x1001; + case MBlaze::RTLBX : return 0x1002; + case MBlaze::RTLBLO : return 0x1003; + case MBlaze::RTLBHI : return 0x1004; + case MBlaze::RPVR0 : return 0x2000; + case MBlaze::RPVR1 : return 0x2001; + case MBlaze::RPVR2 : return 0x2002; + case MBlaze::RPVR3 : return 0x2003; + case MBlaze::RPVR4 : return 0x2004; + case MBlaze::RPVR5 : return 0x2005; + case MBlaze::RPVR6 : return 0x2006; + case MBlaze::RPVR7 : return 0x2007; + case MBlaze::RPVR8 : return 0x2008; + case MBlaze::RPVR9 : return 0x2009; + case MBlaze::RPVR10 : return 0x200A; + case MBlaze::RPVR11 : return 0x200B; default: llvm_unreachable("Unknown register number!"); } return 0; // Not reached @@ -126,6 +150,37 @@ unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) { return 0; // Not reached } +unsigned MBlazeRegisterInfo::getSpecialRegisterFromNumbering(unsigned Reg) { + switch (Reg) { + case 0x0000 : return MBlaze::RPC; + case 0x0001 : return MBlaze::RMSR; + case 0x0003 : return MBlaze::REAR; + case 0x0005 : return MBlaze::RESR; + case 0x0007 : return MBlaze::RFSR; + case 0x000B : return MBlaze::RBTR; + case 0x000D : return MBlaze::REDR; + case 0x1000 : return MBlaze::RPID; + case 0x1001 : return MBlaze::RZPR; + case 0x1002 : return MBlaze::RTLBX; + case 0x1003 : return MBlaze::RTLBLO; + case 0x1004 : return MBlaze::RTLBHI; + case 0x2000 : return MBlaze::RPVR0; + case 0x2001 : return MBlaze::RPVR1; + case 0x2002 : return MBlaze::RPVR2; + case 0x2003 : return MBlaze::RPVR3; + case 0x2004 : return MBlaze::RPVR4; + case 0x2005 : return MBlaze::RPVR5; + case 0x2006 : return MBlaze::RPVR6; + case 0x2007 : return MBlaze::RPVR7; + case 0x2008 : return MBlaze::RPVR8; + case 0x2009 : return MBlaze::RPVR9; + case 0x200A : return MBlaze::RPVR10; + case 0x200B : return MBlaze::RPVR11; + default: llvm_unreachable("Unknown register number!"); + } + return 0; // Not reached +} + unsigned MBlazeRegisterInfo::getPICCallReg() { return MBlaze::R20; } diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.h b/lib/Target/MBlaze/MBlazeRegisterInfo.h index 431a6329b48..839536d4e7b 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.h +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.h @@ -44,6 +44,7 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo { /// MBlaze::RA, return the number that it corresponds to (e.g. 31). static unsigned getRegisterNumbering(unsigned RegEnum); static unsigned getRegisterFromNumbering(unsigned RegEnum); + static unsigned getSpecialRegisterFromNumbering(unsigned RegEnum); /// Get PIC indirect call register static unsigned getPICCallReg(); diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.td b/lib/Target/MBlaze/MBlazeRegisterInfo.td index 40bd7297c39..62593cd30b4 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.td +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.td @@ -82,7 +82,7 @@ let Namespace = "MBlaze" in { def REDR : MBlazeSPRReg<0x000D, "redr">, DwarfRegNum<[38]>; def RPID : MBlazeSPRReg<0x1000, "rpid">, DwarfRegNum<[39]>; def RZPR : MBlazeSPRReg<0x1001, "rzpr">, DwarfRegNum<[40]>; - def RTLBX : MBlazeSPRReg<0x0002, "rtlbx">, DwarfRegNum<[41]>; + def RTLBX : MBlazeSPRReg<0x1002, "rtlbx">, DwarfRegNum<[41]>; def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>; def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>; def RPVR0 : MBlazeSPRReg<0x2000, "rpvr0">, DwarfRegNum<[44]>; @@ -138,3 +138,44 @@ def GPR : RegisterClass<"MBlaze", [i32,f32], 32, } }]; } + +def SPR : RegisterClass<"MBlaze", [i32], 32, + [ + // Reserved + RPC, + RMSR, + REAR, + RESR, + RFSR, + RBTR, + REDR, + RPID, + RZPR, + RTLBX, + RTLBLO, + RTLBHI, + RPVR0, + RPVR1, + RPVR2, + RPVR3, + RPVR4, + RPVR5, + RPVR6, + RPVR7, + RPVR8, + RPVR9, + RPVR10, + RPVR11 + ]> +{ + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + SPRClass::iterator + SPRClass::allocation_order_end(const MachineFunction &MF) const { + // None of the special purpose registers are allocatable. + return end()-24; + } + }]; +} diff --git a/test/MC/MBlaze/mblaze_special.s b/test/MC/MBlaze/mblaze_special.s index 739caf4e433..c55ec277c18 100644 --- a/test/MC/MBlaze/mblaze_special.s +++ b/test/MC/MBlaze/mblaze_special.s @@ -1,7 +1,7 @@ # RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s -# Test to ensure that all FPU instructions can be parsed by the -# assembly parser correctly. +# Test to ensure that all special instructions and special registers can be +# parsed by the assembly parser correctly. # TYPE A: OPCODE RD RA RB FLAGS # BINARY: 011011 00000 00000 00000 00000000000 @@ -9,7 +9,7 @@ # CHECK: mfs # BINARY: 100101 00000 00000 10000 00000000000 # CHECK: encoding: [0x94,0x00,0x80,0x00] - mfs r0, 0x0 + mfs r0, rpc # CHECK: msrclr # BINARY: 100101 00000 100010 000000000000000 @@ -24,7 +24,7 @@ # CHECK: mts # BINARY: 100101 00000 00000 11 00000000000000 # CHECK: encoding: [0x94,0x00,0xc0,0x00] - mts 0x0 , r0 + mts rpc, r0 # CHECK: wdc # BINARY: 100100 00000 00000 00001 00001100100 @@ -45,3 +45,123 @@ # BINARY: 100100 00000 00000 00001 00001101000 # CHECK: encoding: [0x90,0x00,0x08,0x68] wic r0, r1 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000000000 +# CHECK: encoding: [0x94,0x20,0x80,0x00] + mfs r1, rpc + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000000001 +# CHECK: encoding: [0x94,0x20,0x80,0x01] + mfs r1, rmsr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000000011 +# CHECK: encoding: [0x94,0x20,0x80,0x03] + mfs r1, rear + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000000101 +# CHECK: encoding: [0x94,0x20,0x80,0x05] + mfs r1, resr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000000111 +# CHECK: encoding: [0x94,0x20,0x80,0x07] + mfs r1, rfsr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000001011 +# CHECK: encoding: [0x94,0x20,0x80,0x0b] + mfs r1, rbtr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10000 00000001101 +# CHECK: encoding: [0x94,0x20,0x80,0x0d] + mfs r1, redr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10010 00000000000 +# CHECK: encoding: [0x94,0x20,0x90,0x00] + mfs r1, rpid + +# CHECK: mfs +# BINARY: 100101 00001 00000 10010 00000000001 +# CHECK: encoding: [0x94,0x20,0x90,0x01] + mfs r1, rzpr + +# CHECK: mfs +# BINARY: 100101 00001 00000 10010 00000000010 +# CHECK: encoding: [0x94,0x20,0x90,0x02] + mfs r1, rtlbx + +# CHECK: mfs +# BINARY: 100101 00001 00000 10010 00000000100 +# CHECK: encoding: [0x94,0x20,0x90,0x04] + mfs r1, rtlbhi + +# CHECK: mfs +# BINARY: 100101 00001 00000 10010 00000000011 +# CHECK: encoding: [0x94,0x20,0x90,0x03] + mfs r1, rtlblo + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000000 +# CHECK: encoding: [0x94,0x20,0xa0,0x00] + mfs r1, rpvr0 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000001 +# CHECK: encoding: [0x94,0x20,0xa0,0x01] + mfs r1, rpvr1 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000010 +# CHECK: encoding: [0x94,0x20,0xa0,0x02] + mfs r1, rpvr2 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000011 +# CHECK: encoding: [0x94,0x20,0xa0,0x03] + mfs r1, rpvr3 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000100 +# CHECK: encoding: [0x94,0x20,0xa0,0x04] + mfs r1, rpvr4 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000101 +# CHECK: encoding: [0x94,0x20,0xa0,0x05] + mfs r1, rpvr5 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000110 +# CHECK: encoding: [0x94,0x20,0xa0,0x06] + mfs r1, rpvr6 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000000111 +# CHECK: encoding: [0x94,0x20,0xa0,0x07] + mfs r1, rpvr7 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000001000 +# CHECK: encoding: [0x94,0x20,0xa0,0x08] + mfs r1, rpvr8 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000001001 +# CHECK: encoding: [0x94,0x20,0xa0,0x09] + mfs r1, rpvr9 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000001010 +# CHECK: encoding: [0x94,0x20,0xa0,0x0a] + mfs r1, rpvr10 + +# CHECK: mfs +# BINARY: 100101 00001 00000 10100 00000001011 +# CHECK: encoding: [0x94,0x20,0xa0,0x0b] + mfs r1, rpvr11 -- 2.34.1