From 9c45241485c0a1dc6f4ae81440185b54ec118246 Mon Sep 17 00:00:00 2001 From: Matheus Almeida Date: Fri, 31 Jan 2014 13:31:20 +0000 Subject: [PATCH] [mips][msa] Add insert.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200543 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrFormats.td | 13 +++++++++++++ lib/Target/Mips/MipsMSAInstrInfo.td | 6 ++++++ test/CodeGen/Mips/msa/elm_insv.ll | 16 ++++++++++++++++ test/MC/Mips/msa/test_elm_insert_msa64.s | 11 +++++++++++ 4 files changed, 46 insertions(+) create mode 100644 test/MC/Mips/msa/test_elm_insert_msa64.s diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 937898f9d55..3942d05914f 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -341,6 +341,19 @@ class MSA_ELM_INSERT_W_FMT major, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_ELM_INSERT_D_FMT major, bits<6> minor>: MSA64Inst { + bits<6> n; + bits<5> rs; + bits<5> wd; + + let Inst{25-22} = major; + let Inst{21-17} = 0b11100; + let Inst{16} = n{0}; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_I5_FMT major, bits<2> df, bits<6> minor>: MSAInst { bits<5> imm; bits<5> ws; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 1e18af5fc4e..972cc66740e 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -155,6 +155,8 @@ def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; +def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), + (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; class vfsetcc_type : PatFrag<(ops node:$lhs, node:$rhs), @@ -858,6 +860,7 @@ class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; +class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; @@ -2269,6 +2272,8 @@ class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, MSA128HOpnd, GPR32Opnd>; class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, MSA128WOpnd, GPR32Opnd>; +class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, + MSA128DOpnd, GPR64Opnd>; class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE; @@ -3158,6 +3163,7 @@ def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; +def INSERT_D : INSERT_D_ENC, INSERT_D_DESC; // INSERT_FW_PSEUDO defined after INSVE_W // INSERT_FD_PSEUDO defined after INSVE_D diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll index ed5c2e45237..c746e523def 100644 --- a/test/CodeGen/Mips/msa/elm_insv.ll +++ b/test/CodeGen/Mips/msa/elm_insv.ll @@ -5,6 +5,10 @@ ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 @@ -90,10 +94,14 @@ declare <2 x i64> @llvm.mips.insert.d(<2 x i64>, i32, i64) nounwind ; MIPS-ANY: llvm_mips_insert_d_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], 0( ; MIPS32-DAG: ld.w [[R3:\$w[0-9]+]], +; MIPS64-DAG: ld.d [[W1:\$w[0-9]+]], ; MIPS32-DAG: insert.w [[R3]][2], [[R1]] ; MIPS32-DAG: insert.w [[R3]][3], [[R2]] +; MIPS64-DAG: insert.d [[W1]][1], [[R1]] ; MIPS32-DAG: st.w [[R3]], +; MIPS64-DAG: st.d [[W1]], ; MIPS-ANY: .size llvm_mips_insert_d_test ; @llvm_mips_insve_b_ARG1 = global <16 x i8> , align 16 @@ -114,6 +122,8 @@ declare <16 x i8> @llvm.mips.insve.b(<16 x i8>, i32, <16 x i8>) nounwind ; MIPS-ANY: llvm_mips_insve_b_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_b_ARG1)( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_b_ARG3)( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG1)( +; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_b_ARG3)( ; MIPS-ANY-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) ; MIPS-ANY-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) ; MIPS-ANY-DAG: insve.b [[R3]][1], [[R4]][0] @@ -138,6 +148,8 @@ declare <8 x i16> @llvm.mips.insve.h(<8 x i16>, i32, <8 x i16>) nounwind ; MIPS-ANY: llvm_mips_insve_h_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_h_ARG1)( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_h_ARG3)( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG1)( +; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_h_ARG3)( ; MIPS-ANY-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) ; MIPS-ANY-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) ; MIPS-ANY-DAG: insve.h [[R3]][1], [[R4]][0] @@ -162,6 +174,8 @@ declare <4 x i32> @llvm.mips.insve.w(<4 x i32>, i32, <4 x i32>) nounwind ; MIPS-ANY: llvm_mips_insve_w_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_w_ARG1)( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_w_ARG3)( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG1)( +; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_w_ARG3)( ; MIPS-ANY-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) ; MIPS-ANY-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) ; MIPS-ANY-DAG: insve.w [[R3]][1], [[R4]][0] @@ -186,6 +200,8 @@ declare <2 x i64> @llvm.mips.insve.d(<2 x i64>, i32, <2 x i64>) nounwind ; MIPS-ANY: llvm_mips_insve_d_test: ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_insve_d_ARG1)( ; MIPS32-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_insve_d_ARG3)( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG1)( +; MIPS64-DAG: ld [[R2:\$[0-9]+]], %got_disp(llvm_mips_insve_d_ARG3)( ; MIPS-ANY-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) ; MIPS-ANY-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) ; MIPS-ANY-DAG: insve.d [[R3]][1], [[R4]][0] diff --git a/test/MC/Mips/msa/test_elm_insert_msa64.s b/test/MC/Mips/msa/test_elm_insert_msa64.s new file mode 100644 index 00000000000..8196fd0513c --- /dev/null +++ b/test/MC/Mips/msa/test_elm_insert_msa64.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s +# +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ +# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ +# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP +# +# CHECK: insert.d $w1[1], $sp # encoding: [0x79,0x39,0xe8,0x59] + +# CHECKOBJDUMP: insert.d $w1[1], $sp + + insert.d $w1[1], $sp -- 2.34.1