From 9c542eb57dd8928be347db8112871dffe5a48bfd Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Tue, 12 Aug 2014 18:37:38 +0800
Subject: [PATCH] ARM: rockchip: rk312x add cpu axi bus support

---
 arch/arm/boot/dts/rk312x.dtsi | 57 +++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 6561e9314dea..d91db92bcbbd 100755
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -68,6 +68,63 @@
 			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	cpu_axi_bus: cpu_axi_bus {
+		compatible = "rockchip,cpu_axi_bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qos {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			crypto {
+				reg = <0x10128080 0x20>;
+			};
+			core {
+				reg = <0x1012a000 0x20>;
+				rockchip,priority = <3 2>;
+			};
+			peri {
+				reg = <0x1012c000 0x20>;
+			};
+			gpu {
+				reg = <0x1012d000 0x20>;
+			};
+			vpu {
+				reg = <0x1012e000 0x20>;
+			};
+			rga {
+				reg = <0x1012f000 0x20>;
+			};
+			ebc {
+				reg = <0x1012f080 0x20>;
+			};
+			iep {
+				reg = <0x1012f100 0x20>;
+			};
+			lcdc {
+				reg = <0x1012f180 0x20>;
+				rockchip,priority = <3 3>;
+			};
+			vip {
+				reg = <0x1012f200 0x20>;
+			};
+		};
+
+		msch {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			msch@10128000 {
+				reg = <0x10128000 0x20>;
+				rockchip,read-latency = <0x3f>;
+			};
+		};
+	};
+
 	sram: sram@10080000 {
 		compatible = "mmio-sram";
 		reg = <0x10080000 0x2000>;
-- 
2.34.1