From 9c673d9c54881b76b9f642735e603f35935a32fd Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 9 Nov 2015 21:53:58 +0000 Subject: [PATCH] specify triple so Windows bots won't be sad git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252519 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/x86-64-double-precision-shift-left.ll | 2 +- test/CodeGen/X86/x86-64-double-precision-shift-right.ll | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/test/CodeGen/X86/x86-64-double-precision-shift-left.ll b/test/CodeGen/X86/x86-64-double-precision-shift-left.ll index 75e9052c129..7515c46f7ce 100644 --- a/test/CodeGen/X86/x86-64-double-precision-shift-left.ll +++ b/test/CodeGen/X86/x86-64-double-precision-shift-left.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s ; Verify that for the architectures that are known to have poor latency ; double precision shift instructions we generate alternative sequence ; of instructions with lower latencies instead of shld instruction. diff --git a/test/CodeGen/X86/x86-64-double-precision-shift-right.ll b/test/CodeGen/X86/x86-64-double-precision-shift-right.ll index bc2f39ee666..5e3f2294171 100644 --- a/test/CodeGen/X86/x86-64-double-precision-shift-right.ll +++ b/test/CodeGen/X86/x86-64-double-precision-shift-right.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s ; Verify that for the architectures that are known to have poor latency ; double precision shift instructions we generate alternative sequence ; of instructions with lower latencies instead of shrd instruction. -- 2.34.1