From 9d115effdfdde7e7b7ff78eab4c85e5b919aa4b3 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Thu, 11 Jun 2015 10:22:46 +0000 Subject: [PATCH] [mips][microMIPS] Implement ERET and ERETNC instructions http://reviews.llvm.org/D10091 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239522 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrFormats.td | 19 +++++++++++++++++++ lib/Target/Mips/MicroMips32r6InstrInfo.td | 8 ++++++++ lib/Target/Mips/MipsInstrInfo.td | 2 ++ test/MC/Disassembler/Mips/micromips32r6.txt | 19 +++++++++---------- test/MC/Mips/micromips32r6/valid.s | 2 ++ 5 files changed, 40 insertions(+), 10 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 7350b97731b..78ba76d27cb 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -221,3 +221,22 @@ class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6 funct> : MipsR6Inst { let Inst{20-16} = rt; let Inst{15-0} = offset; } + +class ERET_FM_MMR6 : MMR6Arch { + bits<32> Inst; + + let Inst{31-26} = 0x00; + let Inst{25-16} = 0x00; + let Inst{15-6} = 0x3cd; + let Inst{5-0} = 0x3c; +} + +class ERETNC_FM_MMR6 : MMR6Arch { + bits<32> Inst; + + let Inst{31-26} = 0x00; + let Inst{25-17} = 0x00; + let Inst{16-16} = 0x01; + let Inst{15-6} = 0x3cd; + let Inst{5-0} = 0x3c; +} diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 2259d5d7790..ed71c3d9b5f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -40,6 +40,8 @@ class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>; class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>; class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>; class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>; +class ERET_MMR6_ENC : ERET_FM_MMR6<"eret">; +class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">; class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>; class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>; class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>; @@ -164,6 +166,9 @@ class CLO_CLZ_MMR6_DESC_BASE class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>; class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>; +class ERET_MMR6_DESC : ER_FT<"eret">; +class ERETNC_MMR6_DESC : ER_FT<"eretnc">; + class JMP_MMR6_IDX_COMPACT_DESC_BASE : MMR6Arch { @@ -302,6 +307,9 @@ def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6; def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6; def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6; def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6; +def ERET_MMR6 : R6MMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6; +def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC, + ISA_MICROMIPS32R6; def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6; def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6; def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index cf95a194f47..0c154fd64d7 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1281,7 +1281,9 @@ def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def TRAP : TrapBase; def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; +let AdditionalPredicates = [NotInMicroMips] in { def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; +} def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index dee6fbef409..47c4d080f0a 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -32,17 +32,13 @@ 0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332 -# CHECK: balc 14572256 -0xb4 0x37 0x96 0xb8 +0xb4 0x37 0x96 0xb8 # CHECK: balc 14572256 -# CHECK: bc 14572256 -0x94 0x37 0x96 0xb8 +0x94 0x37 0x96 0xb8 # CHECK: bc 14572256 -# CHECK: bitswap $4, $2 -0x00 0x44 0x0b 0x3c +0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2 -# CHECK: cache 1, 8($5) -0x20 0x25 0x60 0x08 +0x20 0x25 0x60 0x08 # CHECK: cache 1, 8($5) 0x01 0x65 0x4b 0x3c # CHECK: clo $11, $5 @@ -52,6 +48,10 @@ 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 +0x00 0x00 0xf3 0x7c # CHECK: eret + +0x00 0x01 0xf3 0x7c # CHECK: eretnc + 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 @@ -78,8 +78,7 @@ 0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234 -# CHECK: pref 1, 8($5) -0x60 0x25 0x20 0x08 +0x60 0x25 0x20 0x08 # CHECK: pref 1, 8($5) 0x00 0x83 0x11 0x40 # CHECK: seleqz $2, $3, $4 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index f4e8eef8f23..94e19f2c46f 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -25,6 +25,8 @@ clz $sp, $gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] div $3, $4, $5 # CHECK: div $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x18] divu $3, $4, $5 # CHECK: divu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x98] + eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] + eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x26,0x0f] -- 2.34.1