From 9d75bc99041c25f82d0cd6cbce0a43913b540c6d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 30 Nov 2015 15:46:47 +0000 Subject: [PATCH] AMDGPU: Don't reserve SCRATCH_PTR input register This hasn't been doing anything since using relocations was added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254304 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIISelLowering.cpp | 16 ++++------------ .../si-instr-info-correct-implicit-operands.ll | 2 +- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 5c67bf80c17..e2c644451b4 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -633,21 +633,13 @@ SDValue SITargetLowering::LowerFormalArguments( unsigned InputPtrRegHi = TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1); - unsigned ScratchPtrReg = - TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR); - unsigned ScratchPtrRegLo = - TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0); - unsigned ScratchPtrRegHi = - TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1); - CCInfo.AllocateReg(InputPtrRegLo); CCInfo.AllocateReg(InputPtrRegHi); - CCInfo.AllocateReg(ScratchPtrRegLo); - CCInfo.AllocateReg(ScratchPtrRegHi); MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass); - MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass); - SIMachineFunctionInfo *MFI = MF.getInfo(); - if (Subtarget->isAmdHsaOS() && MFI->hasDispatchPtr()) { + + const SIMachineFunctionInfo *MFI = MF.getInfo(); + + if (MFI->hasDispatchPtr()) { unsigned DispatchPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR); unsigned DispatchPtrRegLo = diff --git a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll index 0e15bc87865..27a8e70aae1 100644 --- a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll +++ b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -3,7 +3,7 @@ ; register operands in the correct order when modifying the opcode of an ; instruction to V_ADD_I32_e32. -; CHECK: %19 = V_ADD_I32_e32 %13, %12, implicit-def %vcc, implicit %exec +; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: -- 2.34.1