From 9d9dc816d07d42a6a6e0cc3cad7db011ba144796 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 19 Aug 2005 00:41:29 +0000 Subject: [PATCH] add a few missing cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22891 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrInfo.td | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 7b627a79e2c..2ab048fa1c4 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1606,9 +1606,11 @@ def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real] // FSUB reg, mem: Before stackification, these are represented by: // R1 = FSUB* R2, [mem] def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real] - (ops f32mem:$src), "fsub{s} $src">; + (ops f32mem:$src, variable_ops), + "fsub{s} $src">; def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real] - (ops f64mem:$src), "fsub{l} $src">; + (ops f64mem:$src, variable_ops), + "fsub{l} $src">; // ST(0) = ST(0) - [mem16int] //def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int] @@ -1648,9 +1650,11 @@ def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real] // Note that the order of operands does not reflect the operation being // performed. def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0) - (ops f32mem:$src), "fdivr{s} $src">; + (ops f32mem:$src, variable_ops), + "fdivr{s} $src">; def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0) - (ops f64mem:$src), "fdivr{l} $src">; + (ops f64mem:$src, variable_ops), + "fdivr{l} $src">; // ST(0) = [mem16int] / ST(0) //def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0) -- 2.34.1