From 9eabf8c84e0dec0b0c7577d7e4e282b94ed86f4d Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Fri, 28 Mar 2014 17:58:28 +0800
Subject: [PATCH] ARM: rockchip: rk3288 use arch timer

---
 arch/arm/boot/dts/rk3288.dtsi   | 42 +--------------------------------
 arch/arm/mach-rockchip/rk3288.c | 11 +++++++++
 2 files changed, 12 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 91eaa01ee753..399dbccc9bfa 100755
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -177,44 +177,12 @@
 		map-exec;
 	};
 
-/*
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clock-frequency = <24000000>;
 	};
-*/
-
-	timer@ff6b0000 {
-		compatible = "rockchip,timer";
-		reg = <0xff6b0000 0x20>;
-		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,percpu = <0>;
-	};
-
-	timer@ff6b0020 {
-		compatible = "rockchip,timer";
-		reg = <0xff6b0020 0x20>;
-		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,percpu = <1>;
-	};
-
-	timer@ff6b0040 {
-		compatible = "rockchip,timer";
-		reg = <0xff6b0040 0x20>;
-		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,percpu = <2>;
-	};
-
-	timer@ff6b0060 {
-		compatible = "rockchip,timer";
-		reg = <0xff6b0060 0x20>;
-		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,percpu = <3>;
-	};
 
 	timer@ff810000 {
 		compatible = "rockchip,timer";
@@ -223,14 +191,6 @@
 		rockchip,broadcast = <1>;
 	};
 
-	timer@ff810020 {
-		compatible = "rockchip,timer";
-		reg = <0xff810020 0x20>;
-		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,clocksource = <1>;
-		rockchip,count-up = <1>;
-	};
-
 	watchdog:wdt@2004c000 {
 		compatible = "rockchip,watch dog";
 		reg = <0xff800000 0x100>;
diff --git a/arch/arm/mach-rockchip/rk3288.c b/arch/arm/mach-rockchip/rk3288.c
index 9e0bec94191f..6870b9cc7ec8 100755
--- a/arch/arm/mach-rockchip/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288.c
@@ -50,6 +50,7 @@
 	RK_DEVICE(RK3288_SERVICE_##name##_VIRT, RK3288_SERVICE_##name##_PHYS, RK3288_SERVICE_##name##_SIZE)
 
 #define RK3288_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
+#define RK3288_TIMER7_VIRT (RK_TIMER_VIRT + 0x20)
 
 static struct map_desc rk3288_io_desc[] __initdata = {
 	RK3288_DEVICE(CRU),
@@ -83,6 +84,7 @@ static struct map_desc rk3288_io_desc[] __initdata = {
 	RK_DEVICE(RK_GIC_VIRT + RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_PHYS, RK3288_GIC_CPU_SIZE),
 	RK_DEVICE(RK_BOOTRAM_VIRT, RK3288_BOOTRAM_PHYS, RK3288_BOOTRAM_SIZE),
 	RK_DEVICE(RK3288_IMEM_VIRT, RK3288_IMEM_PHYS, SZ_4K),
+	RK_DEVICE(RK_TIMER_VIRT, RK3288_TIMER6_PHYS, RK3288_TIMER_SIZE),
 };
 
 static void __init rk3288_boot_mode_init(void)
@@ -131,6 +133,15 @@ static void __init rk3288_dt_map_io(void)
 	/* disable address remap */
 	writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
 
+	/* enable timer7 for core */
+	writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
+	dsb();
+	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
+	writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
+	dsb();
+	writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
+	dsb();
+
 	rk3288_boot_mode_init();
 }
 
-- 
2.34.1