From 9eda569a74377bdcf8ce6073682fb9a4bd8a82ca Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Tue, 29 Mar 2011 19:49:38 +0000 Subject: [PATCH] A8.6.188 STC, STC2 The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 6 +++--- test/MC/Disassembler/ARM/arm-tests.txt | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 2621b3e3b29..c7960035655 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3430,8 +3430,8 @@ multiclass LdStCop op31_28, bit load, string opc> { } def _OPTION : ACI<(outs), - (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option), - opc, "\tp$cop, cr$CRd, [$base], $option"> { + (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option), + opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { let Inst{31-28} = op31_28; let Inst{24} = 0; // P = 0 let Inst{23} = 1; // U = 1 @@ -3472,7 +3472,7 @@ multiclass LdStCop op31_28, bit load, string opc> { def L_OPTION : ACI<(outs), (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option), - !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> { + !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { let Inst{31-28} = op31_28; let Inst{24} = 0; // P = 0 let Inst{23} = 1; // U = 1 diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 87b7e988b77..65d6206a9e2 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -202,3 +202,9 @@ # CHECK: pli [r3, r1, lsl #2] 0x01 0xf1 0xd3 0xf6 + +# CHECK: stc p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xec + +# CHECK: stc2 p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xfc -- 2.34.1