From 9f6636ff0c6a226dcc4cdeaa78c26686a7bf0cd5 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 19 Mar 2007 07:48:02 +0000 Subject: [PATCH] Fix naming inconsistencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/ARM/ARMInstrInfo.cpp | 4 ++-- lib/Target/ARM/ARMInstrInfo.td | 10 ++++----- lib/Target/ARM/ARMInstrThumb.td | 8 +++---- lib/Target/ARM/ARMRegisterInfo.cpp | 34 +++++++++++++++--------------- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 7c40a712212..8108ee4993b 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -384,7 +384,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N, // We must materialize a zero in a reg! Returning an constant here won't // work since its node is -1 so it won't get added to the selection queue. // Explicitly issue a tMOVri8 node! - Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVri8, MVT::i32, + Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0); return true; } diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 1f4fb0f2b5c..5a016557067 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -672,7 +672,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { // one of the above mentioned nodes. It has to be wrapped because otherwise // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only // be used to form addressing mode. These wrapped nodes will be selected -// into MOVri. +// into MOVi. static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast(Op); diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 36ed76d9616..e89dcf0ac8e 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -50,8 +50,8 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; - case ARM::MOVrr: - case ARM::tMOVrr: + case ARM::MOVr: + case ARM::tMOVr: assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "Invalid ARM MOV instruction"); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b222c5b0ee9..4d2aba744b0 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -710,13 +710,13 @@ def STM : AI4<(ops addrmode4:$addr, reglist:$src1, variable_ops), // Move Instructions. // -def MOVrr : AI1<(ops GPR:$dst, GPR:$src), +def MOVr : AI1<(ops GPR:$dst, GPR:$src), "mov $dst, $src", []>; -def MOVrs : AI1<(ops GPR:$dst, so_reg:$src), +def MOVs : AI1<(ops GPR:$dst, so_reg:$src), "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>; let isReMaterializable = 1 in -def MOVri : AI1<(ops GPR:$dst, so_imm:$src), +def MOVi : AI1<(ops GPR:$dst, so_imm:$src), "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>; // These aren't really mov instructions, but we have to define them this way @@ -728,7 +728,7 @@ def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src), def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src), "movs $dst, $src, asr #1", [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; -def MOVrrx : AI1<(ops GPR:$dst, GPR:$src), +def MOVrx : AI1<(ops GPR:$dst, GPR:$src), "mov $dst, $src, rrx", [(set GPR:$dst, (ARMrrx GPR:$src))]>; @@ -1070,7 +1070,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), // Two piece so_imms. def : ARMPat<(i32 so_imm2part:$src), - (ORRri (MOVri (so_imm2part_1 imm:$src)), + (ORRri (MOVi (so_imm2part_1 imm:$src)), (so_imm2part_2 imm:$src))>; def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index a70bf96fd02..3c7cd03ee75 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -380,7 +380,7 @@ def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>; let isReMaterializable = 1 in -def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src), +def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src), "mov $dst, $src", [(set GPR:$dst, imm0_255:$src)]>; @@ -389,7 +389,7 @@ def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src), // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy', // which is MOV(3). This also supports high registers. -def tMOVrr : TI<(ops GPR:$dst, GPR:$src), +def tMOVr : TI<(ops GPR:$dst, GPR:$src), "cpy $dst, $src", []>; def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs), @@ -544,8 +544,8 @@ def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst), // Two piece imms. def : ThumbPat<(i32 thumb_immshifted:$src), - (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)), + (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), (thumb_immshifted_shamt imm:$src))>; def : ThumbPat<(i32 imm0_255_comp:$src), - (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>; + (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 7d5c88f87b9..2cc9da6967e 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -185,7 +185,7 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, if (RC == ARM::GPRRegisterClass) { MachineFunction &MF = *MBB.getParent(); ARMFunctionInfo *AFI = MF.getInfo(); - BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr), + BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr), DestReg).addReg(SrcReg); } else if (RC == ARM::SPRRegisterClass) BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg); @@ -214,7 +214,7 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, MachineInstr *NewMI = NULL; switch (Opc) { default: break; - case ARM::MOVrr: { + case ARM::MOVr: { if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI) @@ -226,7 +226,7 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI, } break; } - case ARM::tMOVrr: { + case ARM::tMOVr: { if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg)) @@ -448,14 +448,14 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, if (DestReg == ARM::SP) { assert(BaseReg == ARM::SP && "Unexpected!"); LdReg = ARM::R3; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); } if (NumBytes <= 255 && NumBytes >= 0) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); else if (NumBytes < 0 && NumBytes >= -255) { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes); BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else @@ -469,7 +469,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, else MIB.addReg(LdReg).addReg(BaseReg, false, false, true); if (DestReg == ARM::SP) - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } @@ -538,7 +538,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg) .addReg(BaseReg, false, false, true).addImm(ThisVal); } else { - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg) + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg) .addReg(BaseReg, false, false, true); } BaseReg = DestReg; @@ -627,7 +627,7 @@ static void emitThumbConstant(MachineBasicBlock &MBB, int Chunk = (1 << 8) - 1; int ThisVal = (Imm > Chunk) ? Chunk : Imm; Imm -= ThisVal; - BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal); if (Imm > 0) emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII); if (isSub) @@ -690,7 +690,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Offset += MI.getOperand(i+1).getImm(); if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::MOVrr)); + MI.setInstrDescriptor(TII.get(ARM::MOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; @@ -741,7 +741,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (Offset == 0) { // Turn it into a move. - MI.setInstrDescriptor(TII.get(ARM::tMOVrr)); + MI.setInstrDescriptor(TII.get(ARM::tMOVr)); MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.RemoveOperand(i+1); return; @@ -909,12 +909,12 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned TmpReg = ARM::R3; bool UseRR = false; if (ValReg == ARM::R3) { - BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R2, false, false, true); TmpReg = ARM::R2; } if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12) + BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12) .addReg(ARM::R3, false, false, true); if (Opcode == ARM::tSpill) { if (FrameReg == ARM::SP) @@ -934,10 +934,10 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock::iterator NII = next(II); if (ValReg == ARM::R3) - BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2) + BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2) .addReg(ARM::R12, false, false, true); if (TmpReg == ARM::R3 && AFI->isR3LiveIn()) - BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3) + BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3) .addReg(ARM::R12, false, false, true); } else assert(false && "Unexpected opcode!"); @@ -1391,7 +1391,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, if (NumBytes) emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII); else - BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr); } else { if (MBBI->getOpcode() == ARM::tBX_RET && &MBB.front() != MBBI && @@ -1416,7 +1416,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr) .addImm(NumBytes); else - BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr); + BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr); } else if (NumBytes) { emitSPUpdate(MBB, MBBI, NumBytes, false, TII); } -- 2.34.1