From 9f6a386e6a7a8931f824a95f995e76ce32de2e30 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Thu, 15 May 2014 12:18:23 +0000 Subject: [PATCH] [mips][mips64r6] Add bitswap, and dbitswap Summary: Depends on D3728 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3729 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208877 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips32r6InstrFormats.td | 20 ++++++++++++++++++-- lib/Target/Mips/Mips32r6InstrInfo.td | 12 +++++++++++- lib/Target/Mips/Mips64r6InstrInfo.td | 4 +++- test/MC/Mips/mips32r6/valid.s | 1 + test/MC/Mips/mips64r6/valid.s | 2 ++ 5 files changed, 35 insertions(+), 4 deletions(-) diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index b1ab7670f3e..505f0f9b5bf 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -47,8 +47,10 @@ def OPCODE5_DATI : OPCODE5<0b11110>; class OPCODE6 Val> { bits<6> Value = Val; } -def OPCODE6_ALIGN : OPCODE6<0b100000>; -def OPCODE6_DALIGN : OPCODE6<0b100100>; +def OPCODE6_ALIGN : OPCODE6<0b100000>; +def OPCODE6_DALIGN : OPCODE6<0b100100>; +def OPCODE6_BITSWAP : OPCODE6<0b100000>; +def OPCODE6_DBITSWAP : OPCODE6<0b100100>; class FIELD_FMT Val> { bits<5> Value = Val; @@ -118,6 +120,20 @@ class PCREL19_FM : MipsR6Inst { let Inst{18-0} = imm; } +class SPECIAL3_2R_FM : MipsR6Inst { + bits<5> rd; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL3.Value; + let Inst{25-21} = 0b00000; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = 0b00000; + let Inst{5-0} = Operation.Value; +} + class SPECIAL_3R_FM mulop, bits<6> funct> : MipsR6Inst { bits<5> rd; bits<5> rs; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index ec1712585f6..68135c5c1c9 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -63,6 +63,7 @@ class ALIGN_ENC : SPECIAL3_ALIGN_FM; class ALUIPC_ENC : PCREL16_FM; class AUI_ENC : AUI_FM; class AUIPC_ENC : PCREL16_FM; +class BITSWAP_ENC : SPECIAL3_2R_FM; class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>; class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>; class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>; @@ -118,6 +119,15 @@ class AUI_DESC_BASE { class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>; +class BITSWAP_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rd); + dag InOperandList = (ins GPROpnd:$rt); + string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); + list Pattern = []; +} + +class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>; + class DIVMOD_DESC_BASE { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); @@ -179,7 +189,7 @@ def BGEZALC; def BGEZC; def BGTZALC; def BGTZC; -def BITSWAP; // Known as BITREV in DSP ASE +def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; def BLEZALC; def BLEZC; def BLTC; // Also aliased to bgtc with operands swapped diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index bc970436f0c..0f48784898e 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -29,6 +29,7 @@ class DALIGN_ENC : SPECIAL3_DALIGN_FM; class DAUI_ENC : DAUI_FM; class DAHI_ENC : REGIMM_FM; class DATI_ENC : REGIMM_FM; +class DBITSWAP_ENC : SPECIAL3_2R_FM; class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; @@ -48,6 +49,7 @@ class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>; class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>; class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>; class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>; +class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>; class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>; class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>; class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>; @@ -67,7 +69,7 @@ def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; -def DBITSWAP; +def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; // def DLSA; // See MSA diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 54ddd88a360..1ae5c6bb021 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -9,6 +9,7 @@ aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 5ce523a7ab5..257c9e5728f 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -9,10 +9,12 @@ aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] dahi $3,$3,0x5678 # CHECK: dahi $3, $3, 22136 # encoding: [0x04,0x66,0x56,0x78] dati $3,$3,0xabcd # CHECK: dati $3, $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd] + dbitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] -- 2.34.1