From a125cbe839398f7df475e322bdaf150c62a1c8c3 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 20 Mar 2007 22:32:39 +0000 Subject: [PATCH] Updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/README.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index c155e206334..8af07ccffb6 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -470,4 +470,9 @@ More register scavenging work: //===---------------------------------------------------------------------===// -Teach LSR about ARM addressing modes. +More LSR enhancements possible: + +1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged + in a load / store. +2. Allow iv reuse even when a type conversion is required. For example, i8 + and i32 load / store addressing modes are identical. -- 2.34.1