From a1925e6d5d7561f6e22da24ebbb0f4d518860baa Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 5 Nov 2014 17:38:31 +0000 Subject: [PATCH] ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221369 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrInfo.td | 29 ++++++++++++------ lib/Target/Mips/MipsInstrInfo.td | 2 ++ test/CodeGen/Mips/micromips-shift.ll | 44 +++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 9 deletions(-) create mode 100644 test/CodeGen/Mips/micromips-shift.ll diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index fe9d3478a03..b93cf6d19b6 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -140,13 +140,10 @@ class NotMM16 : !strconcat(opstr, "\t$rt, $rs"), [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>; -class ShiftIMM16 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), - !strconcat(opstr, "\t$rd, $rt, $shamt"), - [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], Itin, FrmR>; + !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>; class AddImmUR2 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), @@ -270,10 +267,10 @@ def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, LOGIC_FM_MM16<0x1>; def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>; -def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, shl, - immZExt2Shift, II_SLL>, SHIFT_FM_MM16<0>; -def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, srl, - immZExt2Shift, II_SRL>, SHIFT_FM_MM16<1>; +def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, + SHIFT_FM_MM16<0>; +def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, + SHIFT_FM_MM16<1>; def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16; def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; @@ -508,6 +505,20 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; } +//===----------------------------------------------------------------------===// +// MicroMips arbitrary patterns that map to one or more instructions +//===----------------------------------------------------------------------===// + +def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), + (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; +def : MipsPat<(shl GPR32:$src, immZExt5:$imm), + (SLL_MM GPR32:$src, immZExt5:$imm)>; + +def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), + (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; +def : MipsPat<(srl GPR32:$src, immZExt5:$imm), + (SRL_MM GPR32:$src, immZExt5:$imm)>; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 2962972726e..2562034852b 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1137,10 +1137,12 @@ def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; /// Shift Instructions +let AdditionalPredicates = [NotInMicroMips] in { def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, immZExt5>, SRA_FM<0, 0>; def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, immZExt5>, SRA_FM<2, 0>; +} def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, immZExt5>, SRA_FM<3, 0>; def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, diff --git a/test/CodeGen/Mips/micromips-shift.ll b/test/CodeGen/Mips/micromips-shift.ll new file mode 100644 index 00000000000..8215010bfc7 --- /dev/null +++ b/test/CodeGen/Mips/micromips-shift.ll @@ -0,0 +1,44 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@a = global i32 10, align 4 +@b = global i32 0, align 4 +@c = global i32 10, align 4 +@d = global i32 0, align 4 + +define i32 @shift_left() nounwind { +entry: + %0 = load i32* @a, align 4 + %shl = shl i32 %0, 4 + store i32 %shl, i32* @b, align 4 + + %1 = load i32* @c, align 4 + %shl1 = shl i32 %1, 10 + store i32 %shl1, i32* @d, align 4 + + ret i32 0 +} + +; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + +@i = global i32 10654, align 4 +@j = global i32 0, align 4 +@m = global i32 10, align 4 +@n = global i32 0, align 4 + +define i32 @shift_right() nounwind { +entry: + %0 = load i32* @i, align 4 + %shr = lshr i32 %0, 4 + store i32 %shr, i32* @j, align 4 + + %1 = load i32* @m, align 4 + %shr1 = lshr i32 %1, 10 + store i32 %shr1, i32* @n, align 4 + + ret i32 0 +} + +; CHECK: srl16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} +; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} -- 2.34.1