From a1a3bfca4220d20280a9c50126427aa3e8b8a9c5 Mon Sep 17 00:00:00 2001 From: zsq Date: Sat, 24 Mar 2012 11:29:09 -0700 Subject: [PATCH] add ddr flush process --- drivers/video/rockchip/rga/rga_drv.c | 131 ++++++++++++++++++++-- drivers/video/rockchip/rga/rga_mmu_info.c | 13 ++- 2 files changed, 130 insertions(+), 14 deletions(-) diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c index 4f6ea0bb7319..5279ae34e23d 100755 --- a/drivers/video/rockchip/rga/rga_drv.c +++ b/drivers/video/rockchip/rga/rga_drv.c @@ -49,6 +49,8 @@ #include "rga_mmu_info.h" #include "RGA_API.h" +//#include "bug_320x240_swap0_ABGR8888.h" + #define RGA_TEST 0 @@ -568,20 +570,18 @@ static void rga_try_set_reg(uint32_t num) rga_copy_reg(reg, 0); rga_reg_from_wait_to_run(reg); dmac_flush_range(&rga_service.cmd_buff[0], &rga_service.cmd_buff[28]); - + outer_flush_range(virt_to_phys(&rga_service.cmd_buff[0]),virt_to_phys(&rga_service.cmd_buff[28])); /* * if cmd buf must use mmu * it should be configured before cmd start */ - rga_write((2<<4)|0x1, RGA_MMU_CTRL); + rga_write((2<<4)|0x1, RGA_MMU_CTRL); + rga_write(virt_to_phys(reg->MMU_base)>>2, RGA_MMU_TBL); /* CMD buff */ - rga_write(virt_to_phys(rga_service.cmd_buff) & (~PAGE_MASK), RGA_CMD_ADDR); - - /* master mode */ - rga_write(0x1<<2, RGA_SYS_CTRL); + rga_write(virt_to_phys(rga_service.cmd_buff) & (~PAGE_MASK), RGA_CMD_ADDR); #ifdef RGA_TEST { @@ -593,12 +593,20 @@ static void rga_try_set_reg(uint32_t num) } #endif + /* master mode */ + rga_write(0x1<<2, RGA_SYS_CTRL); + /* All CMD finish int */ rga_write(0x1<<10, RGA_INT); + + //rga_write(1, RGA_MMU_STA_CTRL); /* Start proc */ atomic_set(®->session->done, 0); - rga_write(0x1, RGA_CMD_CTRL); + rga_write(0x1, RGA_CMD_CTRL); + + //while(1) + // printk("mmu_status is %.8x\n", rga_read(RGA_MMU_STA)); #ifdef RGA_TEST { @@ -607,8 +615,7 @@ static void rga_try_set_reg(uint32_t num) for (i=0; i<28; i++) printk("%.8x\n", rga_read(0x100 + i*4)); } - #endif - + #endif } num--; } @@ -746,7 +753,7 @@ static int rga_blit_sync(rga_session *session, struct rga_req *req) atomic_set(®->int_enable, 1); rga_try_set_reg(1); } - + ret_timeout = wait_event_interruptible_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY); if (unlikely(ret_timeout< 0)) { @@ -758,6 +765,8 @@ static int rga_blit_sync(rga_session *session, struct rga_req *req) ret = -ETIMEDOUT; } + + return ret; //printk("rga_blit_sync done******************\n"); @@ -873,11 +882,14 @@ static irqreturn_t rga_irq(int irq, void *dev_id) int int_enable = 0; DBG("rga_irq %d \n", irq); - + + #if RGA_TEST printk("rga_irq is valid\n"); + #endif /*clear INT */ rga_write(rga_read(RGA_INT) | (0x1<<6), RGA_INT); + rga_write(rga_read(RGA_INT) | (0x1<<7), RGA_INT); if(((rga_read(RGA_STATUS) & 0x1) != 0))// idle { @@ -885,6 +897,7 @@ static irqreturn_t rga_irq(int irq, void *dev_id) rga_soft_reset(); } + spin_lock(&rga_service.lock); do @@ -1048,7 +1061,7 @@ static int __devinit rga_drv_probe(struct platform_device *pdev) goto err_clock; } - #endif + data->axi_clk = clk_get(&pdev->dev, "aclk_rga"); if (IS_ERR(data->axi_clk)) @@ -1065,6 +1078,8 @@ static int __devinit rga_drv_probe(struct platform_device *pdev) ret = -ENOENT; goto err_clock; } + + #endif /* map the memory */ @@ -1192,6 +1207,9 @@ static struct platform_driver rga_driver = { }; +//void rga_test_0(void); + + static int __init rga_init(void) { int ret; @@ -1227,6 +1245,8 @@ static int __init rga_init(void) ERR("Platform device register failed (%d).\n", ret); return ret; } + + //rga_test_0(); INFO("Module initialized.\n"); @@ -1251,6 +1271,93 @@ static void __exit rga_exit(void) platform_driver_unregister(&rga_driver); } + +#if 0 +extern uint32_t ABGR8888_320_240_swap0[240][320]; + +unsigned int src_buf[800*480]; +unsigned int dst_buf[800*480]; +unsigned int mmu_buf[1024]; + +void rga_test_0(void) +{ + struct rga_req req; + rga_session session; + unsigned int *src, *dst; + + int i; + + session.pid = current->pid; + INIT_LIST_HEAD(&session.waiting); + INIT_LIST_HEAD(&session.running); + INIT_LIST_HEAD(&session.list_session); + init_waitqueue_head(&session.wait); + /* no need to protect */ + list_add_tail(&session.list_session, &rga_service.session); + atomic_set(&session.task_running, 0); + atomic_set(&session.num_done, 0); + //file->private_data = (void *)session; + + memset(&req, 0, sizeof(struct rga_req)); + src = ABGR8888_320_240_swap0; + dst = dst_buf; + + #if 0 + memset(src_buf, 0x80, 800*480*4); + memset(dst_buf, 0xcc, 800*480*4); + + dmac_flush_range(&src_buf[0], &src_buf[800*480]); + outer_flush_range(virt_to_phys(&src_buf[0]),virt_to_phys(&src_buf[800*480])); + + dmac_flush_range(&dst_buf[0], &dst_buf[800*480]); + outer_flush_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480])); + #endif + + req.src.act_w = 320; + req.src.act_h = 240; + + req.src.vir_w = 320; + req.src.vir_h = 240; + req.src.yrgb_addr = src; + + req.dst.act_w = 320; + req.dst.act_h = 240; + + req.dst.vir_w = 800; + req.dst.vir_h = 480; + req.dst.yrgb_addr = dst; + + req.clip.xmin = 0; + req.clip.xmax = 799; + req.clip.ymin = 0; + req.clip.ymax = 479; + + + + req.render_mode = 0; + req.rotate_mode = 0; + + req.mmu_info.mmu_flag = 0x21; + req.mmu_info.mmu_en = 1; + + rga_blit_sync(&session, &req); + + #if 0 + outer_inv_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480])); + dmac_inv_range(&dst_buf[0], &dst_buf[800*480]); + + for(i=0; i<800*480; i++) + { + if(src[i] != dst[i]) + { + printk("src != dst %d\n", i); + printk("src = %.8x, dst = %.8x \n", src[i], dst[i]); + } + } + #endif +} + +#endif module_init(rga_init); module_exit(rga_exit); diff --git a/drivers/video/rockchip/rga/rga_mmu_info.c b/drivers/video/rockchip/rga/rga_mmu_info.c index dcbd781a51d6..27d3a25d3685 100755 --- a/drivers/video/rockchip/rga/rga_mmu_info.c +++ b/drivers/video/rockchip/rga/rga_mmu_info.c @@ -18,6 +18,7 @@ #include "rga_mmu_info.h" extern rga_service_info rga_service; +extern int mmu_buf[1024]; #define KERNEL_SPACE_VALID 0xc0000000 @@ -413,10 +414,15 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) break; } + printk("MMU_Base addr is %.8x\n", MMU_Base); + printk("CMDStart is %.8x\n",CMDStart); + for(i=0; isrc.yrgb_addr < KERNEL_SPACE_VALID) { ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize); @@ -448,6 +454,8 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) } } } + + printk("MMU_Base[1] = %.8x\n", MMU_Base[1]); if (req->dst.yrgb_addr < KERNEL_SPACE_VALID) { @@ -471,7 +479,6 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) /* zsq * change the buf address in req struct */ - req->mmu_info.base_addr = (virt_to_phys(MMU_Base)>>2); req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); @@ -483,8 +490,10 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) /*record the malloc buf for the cmd end to release*/ reg->MMU_base = MMU_Base; + /* flush data to DDR */ dmac_flush_range(MMU_Base, (MMU_Base + AllSize)); - + outer_flush_range(virt_to_phys(MMU_Base),virt_to_phys(MMU_Base + AllSize)); + status = 0; /* Free the page table */ -- 2.34.1