From a23b3b803e3c65e84d6cadaa221de8b256cbe28d Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 13 Nov 2008 21:21:28 +0000 Subject: [PATCH] Change ScheduleDAG's DAG member from a reference to a pointer, to prepare for the possibility of scheduling without a SelectionDAG being present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59263 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 4 +- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 14 +++---- lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp | 4 +- lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 24 ++++++------ lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 8 ++-- .../SelectionDAG/ScheduleDAGRRList.cpp | 38 +++++++++---------- .../SelectionDAG/SelectionDAGPrinter.cpp | 8 ++-- 7 files changed, 50 insertions(+), 50 deletions(-) diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 9e21b30f376..4facfdab8d2 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -239,7 +239,7 @@ namespace llvm { class ScheduleDAG { public: - SelectionDAG &DAG; // DAG of the current basic block + SelectionDAG *DAG; // DAG of the current basic block MachineBasicBlock *BB; // Current basic block const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information @@ -253,7 +253,7 @@ namespace llvm { std::vector SUnits; // The scheduling units. SmallSet CommuteSet; // Nodes that should be commuted. - ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, + ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm); virtual ~ScheduleDAG() {} diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 1f898dd7265..8ef493b06e9 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -20,7 +20,7 @@ #include "llvm/Support/Debug.h" using namespace llvm; -ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, +ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm) : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) { TII = TM.getInstrInfo(); @@ -76,17 +76,17 @@ void ScheduleDAG::BuildSchedUnits() { // Reserve entries in the vector for each of the SUnits we are creating. This // ensure that reallocation of the vector won't happen, so SUnit*'s won't get // invalidated. - SUnits.reserve(DAG.allnodes_size()); + SUnits.reserve(DAG->allnodes_size()); // During scheduling, the NodeId field of SDNode is used to map SDNodes // to their associated SUnits by holding SUnits table indices. A value // of -1 means the SDNode does not yet have an associated SUnit. - for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(), - E = DAG.allnodes_end(); NI != E; ++NI) + for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), + E = DAG->allnodes_end(); NI != E; ++NI) NI->setNodeId(-1); - for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(), - E = DAG.allnodes_end(); NI != E; ++NI) { + for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), + E = DAG->allnodes_end(); NI != E; ++NI) { if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. continue; @@ -376,7 +376,7 @@ unsigned ScheduleDAG::ComputeMemOperandsEnd(SDNode *Node) { void ScheduleDAG::dumpSchedule() const { for (unsigned i = 0, e = Sequence.size(); i != e; i++) { if (SUnit *SU = Sequence[i]) - SU->dump(&DAG); + SU->dump(DAG); else cerr << "**** NOOP ****\n"; } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp index 4ea29063ab5..fd09b5c77c5 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp @@ -260,7 +260,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op, if (RC && VRC != RC) { cerr << "Register class of operand and regclass of use don't agree!\n"; cerr << "Operand = " << IIOpNum << "\n"; - cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n"; + cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n"; cerr << "MI = "; MI->print(cerr); cerr << "VReg = " << VReg << "\n"; cerr << "VReg RegClass size = " << VRC->getSize() @@ -540,7 +540,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone, switch (Node->getOpcode()) { default: #ifndef NDEBUG - Node->dump(&DAG); + Node->dump(DAG); #endif assert(0 && "This target-independent node should have been selected!"); break; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index d205f3d0903..c146e15840f 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -71,7 +71,7 @@ private: std::vector LiveRegCycles; public: - ScheduleDAGFast(SelectionDAG &dag, MachineBasicBlock *bb, + ScheduleDAGFast(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm) : ScheduleDAG(dag, bb, tm) {} @@ -125,7 +125,7 @@ void ScheduleDAGFast::Schedule() { BuildSchedUnits(); DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(&DAG)); + SUnits[su].dumpAll(DAG)); // Execute the actual scheduling loop. ListScheduleBottomUp(); @@ -150,7 +150,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain, #ifndef NDEBUG if (PredSU->NumSuccsLeft < 0) { cerr << "*** List scheduling failed! ***\n"; - PredSU->dump(&DAG); + PredSU->dump(DAG); cerr << " has been released too many times!\n"; assert(0); } @@ -167,7 +167,7 @@ void ScheduleDAGFast::ReleasePred(SUnit *PredSU, bool isChain, /// the Available queue. void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(&DAG)); + DEBUG(SU->dump(DAG)); SU->Cycle = CurCycle; // Bottom up: release predecessors @@ -246,7 +246,7 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { if (TryUnfold) { SmallVector NewNodes; - if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) + if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes)) return NULL; DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; @@ -257,9 +257,9 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { unsigned NumVals = N->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues(); for (unsigned i = 0; i != NumVals; ++i) - DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); - DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), - SDValue(LoadNode, 1)); + DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); + DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), + SDValue(LoadNode, 1)); SUnit *NewSU = CreateNewSUnit(N); assert(N->getNodeId() == -1 && "Node already inserted!"); @@ -515,7 +515,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() { unsigned CurCycle = 0; // Add root to Available queue. if (!SUnits.empty()) { - SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; + SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); RootSU->isAvailable = true; AvailableQueue.push(RootSU); @@ -625,14 +625,14 @@ void ScheduleDAGFast::ListScheduleBottomUp() { } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } if (SUnits[i].NumSuccsLeft != 0) { if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has successors left!\n"; AnyNotSched = true; } @@ -654,5 +654,5 @@ llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, const TargetMachine *TM, MachineBasicBlock *BB, bool) { - return new ScheduleDAGFast(*DAG, BB, *TM); + return new ScheduleDAGFast(DAG, BB, *TM); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 178c3f6ca4e..de9ae72ff3e 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -62,7 +62,7 @@ private: HazardRecognizer *HazardRec; public: - ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb, + ScheduleDAGList(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm, SchedulingPriorityQueue *availqueue, HazardRecognizer *HR) @@ -142,7 +142,7 @@ void ScheduleDAGList::ReleaseSucc(SUnit *SuccSU, bool isChain) { /// the Available queue. void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(&DAG)); + DEBUG(SU->dump(DAG)); Sequence.push_back(SU); SU->Cycle = CurCycle; @@ -264,7 +264,7 @@ void ScheduleDAGList::ListScheduleTopDown() { if (SUnits[i].NumPredsLeft != 0) { if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } @@ -543,7 +543,7 @@ ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, const TargetMachine *TM, MachineBasicBlock *BB, bool Fast) { - return new ScheduleDAGList(*DAG, BB, *TM, + return new ScheduleDAGList(DAG, BB, *TM, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 3d90a092a0f..99c9a22a9e8 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -74,7 +74,7 @@ private: std::vector LiveRegCycles; public: - ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb, + ScheduleDAGRRList(SelectionDAG *dag, MachineBasicBlock *bb, const TargetMachine &tm, bool isbottomup, bool f, SchedulingPriorityQueue *availqueue) : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), Fast(f), @@ -186,7 +186,7 @@ void ScheduleDAGRRList::Schedule() { BuildSchedUnits(); DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) - SUnits[su].dumpAll(&DAG)); + SUnits[su].dumpAll(DAG)); if (!Fast) { CalculateDepths(); CalculateHeights(); @@ -278,7 +278,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, #ifndef NDEBUG if (PredSU->NumSuccsLeft < 0) { cerr << "*** List scheduling failed! ***\n"; - PredSU->dump(&DAG); + PredSU->dump(DAG); cerr << " has been released too many times!\n"; assert(0); } @@ -295,7 +295,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, /// the Available queue. void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(&DAG)); + DEBUG(SU->dump(DAG)); SU->Cycle = CurCycle; AvailableQueue->ScheduledNode(SU); @@ -362,7 +362,7 @@ void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { /// its predecessor states to reflect the change. void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { DOUT << "*** Unscheduling [" << SU->Cycle << "]: "; - DEBUG(SU->dump(&DAG)); + DEBUG(SU->dump(DAG)); AvailableQueue->UnscheduledNode(SU); @@ -651,7 +651,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { if (TryUnfold) { SmallVector NewNodes; - if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) + if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes)) return NULL; DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; @@ -662,9 +662,9 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { unsigned NumVals = N->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues(); for (unsigned i = 0; i != NumVals; ++i) - DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); - DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), - SDValue(LoadNode, 1)); + DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); + DAG->ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), + SDValue(LoadNode, 1)); // LoadNode may already exist. This can happen when there is another // load from the same location and producing the same type of value @@ -933,7 +933,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { unsigned CurCycle = 0; // Add root to Available queue. if (!SUnits.empty()) { - SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; + SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()]; assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); RootSU->isAvailable = true; AvailableQueue->push(RootSU); @@ -1079,14 +1079,14 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } if (SUnits[i].NumSuccsLeft != 0) { if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has successors left!\n"; AnyNotSched = true; } @@ -1119,7 +1119,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain, #ifndef NDEBUG if (SuccSU->NumPredsLeft < 0) { cerr << "*** List scheduling failed! ***\n"; - SuccSU->dump(&DAG); + SuccSU->dump(DAG); cerr << " has been released too many times!\n"; assert(0); } @@ -1137,7 +1137,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain, /// the Available queue. void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { DOUT << "*** Scheduling [" << CurCycle << "]: "; - DEBUG(SU->dump(&DAG)); + DEBUG(SU->dump(DAG)); SU->Cycle = CurCycle; AvailableQueue->ScheduledNode(SU); @@ -1201,14 +1201,14 @@ void ScheduleDAGRRList::ListScheduleTopDown() { } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } if (SUnits[i].NumPredsLeft != 0) { if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; - SUnits[i].dump(&DAG); + SUnits[i].dump(DAG); cerr << "has predecessors left!\n"; AnyNotSched = true; } @@ -1885,7 +1885,7 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, MachineBasicBlock *BB, bool Fast) { if (Fast) - return new ScheduleDAGRRList(*DAG, BB, *TM, true, true, + return new ScheduleDAGRRList(DAG, BB, *TM, true, true, new BURegReductionFastPriorityQueue()); const TargetInstrInfo *TII = TM->getInstrInfo(); @@ -1894,7 +1894,7 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); ScheduleDAGRRList *SD = - new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ); + new ScheduleDAGRRList(DAG, BB, *TM, true, false, PQ); PQ->setScheduleDAG(SD); return SD; } @@ -1904,6 +1904,6 @@ llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, const TargetMachine *TM, MachineBasicBlock *BB, bool Fast) { - return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast, + return new ScheduleDAGRRList(DAG, BB, *TM, false, Fast, new TDRegReductionPriorityQueue()); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 9cca6720460..22791d3dc76 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -387,7 +387,7 @@ namespace llvm { template<> struct DOTGraphTraits : public DefaultDOTGraphTraits { static std::string getGraphName(const ScheduleDAG *G) { - return DOTGraphTraits::getGraphName(&G->DAG); + return DOTGraphTraits::getGraphName(G->DAG); } static bool renderGraphFromBottomUp() { @@ -421,7 +421,7 @@ namespace llvm { static void addCustomGraphFeatures(ScheduleDAG *G, GraphWriter &GW) { GW.emitSimpleNode(0, "plaintext=circle", "GraphRoot"); - const SDNode *N = G->DAG.getRoot().getNode(); + const SDNode *N = G->DAG->getRoot().getNode(); if (N && N->getNodeId() != -1) GW.emitEdge(0, -1, &G->SUnits[N->getNodeId()], -1, "color=blue,style=dashed"); @@ -435,11 +435,11 @@ std::string DOTGraphTraits::getNodeLabel(const SUnit *SU, for (unsigned i = 0; i < SU->FlaggedNodes.size(); ++i) { Op += DOTGraphTraits::getNodeLabel(SU->FlaggedNodes[i], - &G->DAG) + "\n"; + G->DAG) + "\n"; } if (SU->Node) - Op += DOTGraphTraits::getNodeLabel(SU->Node, &G->DAG); + Op += DOTGraphTraits::getNodeLabel(SU->Node, G->DAG); else Op += ""; -- 2.34.1