From a26bf0123e79d25fae6175af3e99a400a3b836ec Mon Sep 17 00:00:00 2001 From: Aiyoujun Date: Fri, 18 Mar 2016 17:04:15 +0800 Subject: [PATCH] ARM: dts: rk3366: add smart card reader controller's resource define. Change-Id: Icb21dc6b529e2791414f19a915085437332736df Signed-off-by: Aiyoujun --- arch/arm64/boot/dts/rockchip/rk3366.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi index 071cba065437..9d9c36c68059 100644 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi @@ -227,6 +227,19 @@ status = "disabled"; }; + scr: rkscr@ff1d0000 { + compatible = "rockchip-scr"; + reg = <0x0 0xff1d0000 0x0 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>; + clocks = <&cru PCLK_SIM>; + clock-names = "g_pclk_sim_card"; + status = "disabled"; + }; + sdmmc: rksdmmc@ff400000 { compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc"; clock-freq-min-max = <400000 150000000>; @@ -1245,6 +1258,28 @@ }; }; + scr { + scr_clk: scr-clk { + rockchip,pins = + <5 8 RK_FUNC_2 &pcfg_pull_none>; + }; + + scr_io: scr-io { + rockchip,pins = + <5 9 RK_FUNC_2 &pcfg_pull_up>; + }; + + scr_rst: scr-rst { + rockchip,pins = + <5 10 RK_FUNC_1 &pcfg_pull_none>; + }; + + scr_detect: scr-detect { + rockchip,pins = + <5 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = -- 2.34.1