From a40d4ae47869167fc8cdfa88c041dca93154ef04 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Wed, 25 Feb 2015 18:06:45 +0000 Subject: [PATCH] [PowerPC] Cleanup unused target-specific SDAG nodes We had somehow accumulated a few target-specific SDAG nodes dealing with PPC64 TOC access that were referenced only in TableGen patterns. The associated (pseudo-)instructions are used, but are being generated directly. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230518 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 3 --- lib/Target/PowerPC/PPCISelLowering.h | 17 +---------------- lib/Target/PowerPC/PPCInstr64Bit.td | 16 ++++++---------- lib/Target/PowerPC/PPCInstrInfo.td | 6 ------ 4 files changed, 7 insertions(+), 35 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 4f3a625633f..f59cad50152 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -991,9 +991,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; case PPCISD::CR6SET: return "PPCISD::CR6SET"; case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; - case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; - case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; - case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT"; case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 47d9c68f538..a2a824106b1 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -192,7 +192,7 @@ namespace llvm { PPC32_GOT, /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and - /// local dynamic TLS on PPC32. + /// local dynamic TLS on PPC32. PPC32_PICGOT, /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec @@ -325,21 +325,6 @@ namespace llvm { /// destination 64-bit register. LFIWZX, - /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, - /// produces an ADDIS8 instruction that adds the TOC base register to - /// sym\@toc\@ha. - ADDIS_TOC_HA, - - /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, - /// produces a LD instruction with base register G8RReg and offset - /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. - LD_TOC_L, - - /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces - /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. - /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. - ADDI_TOC_L, - /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. /// Maps directly to an lxvd2x instruction that will be followed by /// an xxswapd. diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 449c8e3ee5f..69c0d7d626f 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -863,19 +863,15 @@ def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), } // Support for medium and large code model. +let hasSideEffects = 0 in { def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), - "#ADDIStocHA", - [(set i64:$rD, - (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, - isPPC64; + "#ADDIStocHA", []>, isPPC64; +let mayLoad = 1 in def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), - "#LDtocL", - [(set i64:$rD, - (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; + "#LDtocL", []>, isPPC64; def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), - "#ADDItocL", - [(set i64:$rD, - (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; + "#ADDItocL", []>, isPPC64; +} // Support for thread-local storage. def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index c2c53355b6e..cee58a6bfab 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -230,12 +230,6 @@ def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, [SDNPHasChain, SDNPMayStore]>; -// Instructions to support medium and large code model -def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; -def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; -def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; - - // Instructions to support dynamic alloca. def SDTDynOp : SDTypeProfile<1, 2, []>; def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; -- 2.34.1