From a5981d074998abeed694ad5bfc320d112d3da174 Mon Sep 17 00:00:00 2001 From: lintao Date: Tue, 16 Sep 2014 09:57:21 +0800 Subject: [PATCH] mmc: guarantee enough time-gap between any two sequential tuning cmd Signed-off-by: lintao --- drivers/mmc/host/dw_mmc-rockchip.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index cfbbcccac732..b9aa0a9ab246 100755 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -395,7 +395,6 @@ re_phase: dw_mci_rockchip_load_signal_integrity(host, SLEW_RATE_SLOW, default_drv); /* Loop degree from 0 ~ 270 */ for(start_degree = SDMMC_SHIFT_DEGREE_0; start_degree < SDMMC_SHIFT_DEGREE_270; start_degree++){ - dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, start_degree); if(0 == __dw_mci_rockchip_execute_tuning(slot, opcode, blk_test, blksz)){ if(!memcmp(blk_pattern, blk_test, blksz)){ @@ -403,8 +402,16 @@ re_phase: candidates_degree[index] = start_degree; index++; } - } - + } + /* eMMC spec does not require a delay between tuning cycles + * but eMMC should be guaranteed to complete a sequence of 40 times CMD21 + * withnin 150ms, some eMMC may limit 4ms gap between any two sequential CMD21 + */ + if (opcode == MMC_SEND_TUNING_BLOCK) + mdelay(1); + else + /* MMC_SEND_TUNING_BLOCK_HS200 */ + mdelay(5); } MMC_DBG_BOOT_FUNC(host->mmc,"\n execute tuning: candidates_degree = %s \t%s \t%s \t%s[%s]", -- 2.34.1