From a5b0564f691b2134764d7e19fe625e1c96fa400a Mon Sep 17 00:00:00 2001 From: hjc Date: Tue, 11 Mar 2014 09:40:16 +0800 Subject: [PATCH] rk3288 lcdc: win0/1/2/3 test at fpga ok --- drivers/video/rockchip/lcdc/Kconfig | 10 - drivers/video/rockchip/lcdc/rk3288_lcdc.c | 6287 +++++++++++---------- drivers/video/rockchip/lcdc/rk3288_lcdc.h | 3095 +++++----- drivers/video/rockchip/rk_fb.c | 30 +- include/linux/rk_fb.h | 15 +- include/linux/rk_screen.h | 1 + 6 files changed, 4700 insertions(+), 4738 deletions(-) diff --git a/drivers/video/rockchip/lcdc/Kconfig b/drivers/video/rockchip/lcdc/Kconfig index 2b3907a6e66f..b45cdec8b772 100755 --- a/drivers/video/rockchip/lcdc/Kconfig +++ b/drivers/video/rockchip/lcdc/Kconfig @@ -94,13 +94,3 @@ config LCDC_RK3288 depends on FB_ROCKCHIP help Driver for rk3288 lcdc.There are two lcd controllers on rk3288 -config LCDC0_RK3288 - bool "lcdc0 support" - depends on LCDC_RK3288 - help - Support rk3288 lcdc0 if you say y here -config LCDC1_RK3288 - bool "lcdc1 support" - depends on LCDC_RK3288 - help - Support rk3288 lcdc1 if you say y here diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.c b/drivers/video/rockchip/lcdc/rk3288_lcdc.c index 1bc6972b0307..5c5a23295e55 100755 --- a/drivers/video/rockchip/lcdc/rk3288_lcdc.c +++ b/drivers/video/rockchip/lcdc/rk3288_lcdc.c @@ -1,3112 +1,3175 @@ -/* - * drivers/video/rockchip/lcdc/rk3288_lcdc.c - * - * Copyright (C) 2014 ROCKCHIP, Inc. - *Author:hjc - *This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "rk3288_lcdc.h" - -#if defined(CONFIG_HAS_EARLYSUSPEND) -#include -#endif - -static int dbg_thresd; -module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); - -#define DBG(level, x...) do { \ - if (unlikely(dbg_thresd >= level)) \ - printk(KERN_INFO x); } while (0) - -//#define WAIT_FOR_SYNC 1 - -static int rk3288_lcdc_get_id(u32 phy_base) -{ - if (cpu_is_rk3288()) { - if (phy_base == 0xff940000)//vop lite - return 0; - else if (phy_base == 0xff930000)//vop big - return 1; - else - return -EINVAL; - } else { - pr_err("un supported platform \n"); - return -EINVAL; - } - -} - -static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) -{ - int i = 0; - int __iomem *c; - int v; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - - return 0; - -} - -static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev) -{ - - if (!lcdc_dev->clk_on) { - clk_prepare_enable(lcdc_dev->hclk); - clk_prepare_enable(lcdc_dev->dclk); - clk_prepare_enable(lcdc_dev->aclk); - //clk_enable(lcdc_dev->pd); - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 1; - spin_unlock(&lcdc_dev->reg_lock); - } - - return 0; -} - -static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev) -{ - if (lcdc_dev->clk_on) { - spin_lock(&lcdc_dev->reg_lock); - lcdc_dev->clk_on = 0; - spin_unlock(&lcdc_dev->reg_lock); - mdelay(25); - clk_disable_unprepare(lcdc_dev->dclk); - clk_disable_unprepare(lcdc_dev->hclk); - clk_disable_unprepare(lcdc_dev->aclk); - //clk_disable(lcdc_dev->pd); - } - - return 0; -} - -static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev) -{ - u32 mask, val; - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN | - m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN; - val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) | - v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - - mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR | - m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR; - val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) | - v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - - mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | - m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN | - m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | - m_POST_BUF_EMPTY_INTR_EN; - val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) | - v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) | - v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) | - v_PWM_GEN_INTR_EN(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); - - mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR | - m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR | - m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR | - m_POST_BUF_EMPTY_INTR_CLR; - val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) | - v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) | - v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) | - v_PWM_GEN_INTR_CLR(0); - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); - return 0; -} -static void rk3288_lcdc_reg_dump(struct lcdc_device *lcdc_dev) -{ - int *cbase = (int *)lcdc_dev->regs; - int *regsbak = (int *)lcdc_dev->regsbak; - int i, j; - - printk("back up reg:\n"); - for (i = 0; i <= (0x300 >> 4); i++) { - for (j = 0; j < 4; j++) - printk("%08x ", *(regsbak + i * 4 + j)); - printk("\n"); - } - - printk("lcdc reg:\n"); - for (i = 0; i <= (0x300 >> 4); i++) { - for (j = 0; j < 4; j++) - printk("%08x ", readl_relaxed(cbase + i * 4 + j)); - printk("\n"); - } - -} - -/********do basic init*********/ -static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) -{ - int v; - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - if (lcdc_dev->pre_init) - return 0; - - if (lcdc_dev->id == 0) { - //lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); - lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc0"); - lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc0"); - lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc0"); - } else if (lcdc_dev->id == 1) { - //lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); - lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc1"); - lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc1"); - lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc1"); - } else { - dev_err(lcdc_dev->dev, "invalid lcdc device!\n"); - return -EINVAL; - } - if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) || - (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { - dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", - lcdc_dev->id); - } - - /*uboot display has enabled lcdc in boot */ - if (!support_uboot_display()) { - rk_disp_pwr_enable(dev_drv); - rk3288_lcdc_clk_enable(lcdc_dev); - } else { - lcdc_dev->clk_on = 1; - } - - //rk3288_lcdc_read_reg_defalut_cfg(lcdc_dev); - rk3288_lcdc_reg_dump(lcdc_dev); - - if (lcdc_dev->pwr18 == true) { - v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/ - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); - } else { - v = 0x00010000; - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); - } - - lcdc_set_bit(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN); - lcdc_cfg_done(lcdc_dev); - lcdc_dev->pre_init = true; - - return 0; -} - -static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev) -{ - - - rk3288_lcdc_disable_irq(lcdc_dev); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - lcdc_dev->clk_on = 0; - lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - } - mdelay(1); -} -static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - struct rk_lcdc_win *win; - u32 colorkey_r,colorkey_g,colorkey_b; - int i,key_val; - for(i=0;i<4;i++){ - win = dev_drv->win[i]; - key_val = win->color_key_val; - colorkey_r = (key_val & 0xff)<<2; - colorkey_g = ((key_val>>8)&0xff)<<12; - colorkey_b = ((key_val>>16)&0xff)<<22; - key_val = colorkey_r | colorkey_g | colorkey_b; - switch(i){ - case 0: - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val); - break; - case 1: - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val); - break; - case 2: - lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val); - break; - case 3: - lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val); - break; - default: - break; - } - } - return 0; -} - -static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - struct alpha_config alpha_config; - - u32 mask, val; - int ppixel_alpha,global_alpha; - u32 src_alpha_ctl,dst_alpha_ctl; - ppixel_alpha = ((win->format == ARGB888)||(win->format == ABGR888)) ? 1 : 0; - global_alpha = (win->g_alpha_val == 0) ? 0 : 1; - alpha_config.src_global_alpha_val = win->g_alpha_val; - switch(win->alpha_mode){ - case AB_USER_DEFINE: - break; - case AB_CLEAR: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_SRC: - alpha_config.src_factor_mode=AA_ONE; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_ONE; - break; - case AB_SRC_OVER: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_ONE; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_DST_OVER: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_ONE; - break; - case AB_SRC_IN: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST_IN: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_SRC; - break; - case AB_SRC_OUT: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_ZERO; - break; - case AB_DST_OUT: - alpha_config.src_factor_mode=AA_ZERO; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_SRC_ATOP: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_DST_ATOP: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_SRC; - break; - case XOR: - alpha_config.src_color_mode=AA_SRC_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_INVERSE; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - case AB_SRC_OVER_GLOBAL: - alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL; - alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL; - alpha_config.src_factor_mode=AA_SRC_GLOBAL; - alpha_config.dst_factor_mode=AA_SRC_INVERSE; - break; - default: - printk("alpha mode error\n"); - break; - } - if((ppixel_alpha == 1)&&(global_alpha == 1)){ - alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; - }else if(ppixel_alpha == 1){ - alpha_config.src_global_alpha_mode = AA_PER_PIX; - }else if(global_alpha == 1){ - alpha_config.src_global_alpha_mode = AA_GLOBAL; - }else{ - printk("alpha_en should be 0\n"); - } - alpha_config.src_alpha_mode = AA_STRAIGHT; - alpha_config.src_alpha_sel = AA_NO_SAT; - - switch(win_id){ - case 0: - src_alpha_ctl = 0x60; - dst_alpha_ctl = 0x64; - break; - case 1: - src_alpha_ctl = 0xa0; - dst_alpha_ctl = 0xa4; - break; - case 2: - src_alpha_ctl = 0xdc; - dst_alpha_ctl = 0xec; - break; - case 3: - src_alpha_ctl = 0x12c; - dst_alpha_ctl = 0x13c; - break; - } - mask = m_WIN0_DST_FACTOR_M0; - val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode); - lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val); - mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 | - m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 | - m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0| - m_WIN0_SRC_GLOBAL_ALPHA; - val = v_WIN0_SRC_ALPHA_EN(1) | - v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) | - v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) | - v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) | - v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) | - v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val); - lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val); - - return 0; -} - -static int rk3288_win_full_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, off; - off = win_id * 0x40; - - if(win->state == 1){ - mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 | - m_WIN0_LB_MODE | m_WIN0_RB_SWAP; - val = v_WIN0_EN(win->state) | v_WIN0_DATA_FMT(win->fmt_cfg) | - v_WIN0_FMT_10(win->fmt_10) | - v_WIN0_LB_MODE(win->win_lb_mode) | v_WIN0_RB_SWAP(win->swap_rb); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); - - mask = m_WIN0_BIC_COE_SEL | - m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 | - m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT4 | - m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE | - m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE | - m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE | - m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE | - m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE; - val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) | - v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) | - v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) | - v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) | - v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) | - v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) | - v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) | - v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) | - v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) | - v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) | - v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) | - v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) | - v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) | - v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) | - v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val); - - val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) | - v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride); - lcdc_writel(lcdc_dev, WIN0_VIR+off, val); - lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr); - lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr); - val = v_WIN0_ACT_WIDTH(win->area[0].xact) | - v_WIN0_ACT_HEIGHT(win->area[0].yact); - lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val); - - val = v_WIN0_DSP_WIDTH(win->area[0].xsize) | - v_WIN0_DSP_HEIGHT(win->area[0].ysize); - lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val); - - val = v_WIN0_DSP_XST(win->area[0].dsp_stx) | - v_WIN0_DSP_YST(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val); - - val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | - v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val); - - val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | - v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); - lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val); - if(win->alpha_en == 1) - rk3288_lcdc_alpha_cfg(dev_drv,win_id); - else{ - mask = m_WIN0_SRC_ALPHA_EN; - val = v_WIN0_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val); - } - //offset alpha src dst - }else{ - mask = m_WIN0_EN; - val = v_WIN0_EN(win->state); - lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); - } - return 0; -} - -static int rk3288_win_lite_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_lcdc_win *win = dev_drv->win[win_id]; - unsigned int mask, val, off; - off = (win_id-2) * 0x50; - - if(win->state == 1){ - mask = m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP; - val = v_WIN2_EN(1) | v_WIN2_DATA_FMT(win->state) | - v_WIN2_RB_SWAP(win->swap_rb); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - //area 0 - if(win->area[0].state == 1){ - mask = m_WIN2_MST0_EN; - val = v_WIN2_MST0_EN(1); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE0; - val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); - - lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr); - val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) | - v_WIN2_DSP_HEIGHT0(win->area[0].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val); - val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) | - v_WIN2_DSP_YST0(win->area[0].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val); - }else{ - mask = m_WIN2_MST0_EN; - val = v_WIN2_MST0_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - } - //area 1 - if(win->area[1].state == 1){ - mask = m_WIN2_MST1_EN; - val = v_WIN2_MST1_EN(1); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE1; - val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); - - lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr); - val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) | - v_WIN2_DSP_HEIGHT1(win->area[1].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val); - val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) | - v_WIN2_DSP_YST1(win->area[1].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val); - }else{ - mask = m_WIN2_MST1_EN; - val = v_WIN2_MST1_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - } - //area 2 - if(win->area[2].state == 1){ - mask = m_WIN2_MST2_EN; - val = v_WIN2_MST2_EN(1); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE2; - val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); - - lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr); - val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) | - v_WIN2_DSP_HEIGHT2(win->area[2].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val); - val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) | - v_WIN2_DSP_YST2(win->area[2].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val); - }else{ - mask = m_WIN2_MST2_EN; - val = v_WIN2_MST2_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - } - //area 3 - if(win->area[3].state == 1){ - mask = m_WIN2_MST3_EN; - val = v_WIN2_MST3_EN(1); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - - mask = m_WIN2_VIR_STRIDE3; - val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride); - lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); - - lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr); - val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) | - v_WIN2_DSP_HEIGHT3(win->area[3].ysize); - lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val); - val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) | - v_WIN2_DSP_YST3(win->area[3].dsp_sty); - lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val); - }else{ - mask = m_WIN2_MST3_EN; - val = v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); - } - - if(win->alpha_en == 1) - rk3288_lcdc_alpha_cfg(dev_drv,win_id); - else{ - mask = m_WIN2_SRC_ALPHA_EN; - val = v_WIN2_SRC_ALPHA_EN(0); - lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val); - } - }else{ - mask = m_WIN2_EN | m_WIN2_MST0_EN | - m_WIN2_MST0_EN | m_WIN2_MST2_EN | - m_WIN2_MST3_EN; - val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) | - v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | - v_WIN2_MST3_EN(0); - lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val); - } - return 0; -} - -static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int timeout; - unsigned long flags; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - rk3288_win_full_reg_update(dev_drv,0); - rk3288_win_full_reg_update(dev_drv,1); - rk3288_win_lite_reg_update(dev_drv,2); - rk3288_win_lite_reg_update(dev_drv,3); - rk3288_lcdc_post_cfg(dev_drv); - } - spin_unlock(&lcdc_dev->reg_lock); - - if (dev_drv->wait_fs) { - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies - (dev_drv->cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } - } - DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); - return 0; - -} - -static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev) -{ - memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x84); - return 0; -} - -static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total,v_total; - u16 post_hsd_en,post_vsd_en; - u16 post_dsp_hact_st,post_dsp_hact_end; - u16 post_dsp_vact_st,post_dsp_vact_end; - u16 post_h_fac,post_v_fac; - - h_total = screen->mode.hsync_len+screen->mode.left_margin + - x_res + screen->mode.right_margin; - v_total = screen->mode.vsync_len+screen->mode.upper_margin + - y_res + screen->mode.lower_margin; - - if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){ - post_hsd_en = 1; - if(screen->post_dsp_stx + screen->post_xsize > h_total){ - printk("post:stx[%d]+xsize[%d] > h_total[%d]\n", - screen->post_dsp_stx,screen->post_xsize, - h_total); - screen->post_dsp_stx = h_total - screen->post_xsize; - } - if(screen->x_mirror == 0){ - post_dsp_hact_st=screen->post_dsp_stx; - post_dsp_hact_end = screen->post_dsp_stx + screen->post_xsize; - }else{ - post_dsp_hact_st = h_total - screen->post_dsp_stx; - post_dsp_hact_end = post_dsp_hact_st - screen->post_xsize; - } - - post_h_fac = - GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize); - }else{ - post_hsd_en = 0; - post_h_fac = 0x100; - } - - if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){ - post_vsd_en = 1; - if(screen->post_dsp_sty + screen->post_ysize > v_total){ - printk("post:sty[%d]+ysize[%d] > v_total[%d]\n", - screen->post_dsp_sty,screen->post_ysize, - v_total); - screen->post_dsp_sty = v_total - screen->post_ysize; - } - - if(screen->y_mirror == 0){ - post_dsp_vact_st = screen->post_dsp_sty; - post_dsp_vact_end = screen->post_dsp_sty + screen->post_ysize; - }else{ - post_dsp_vact_st = v_total - screen->post_dsp_sty; - post_dsp_vact_end = post_dsp_vact_st - screen->post_ysize; - } - - post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize); - }else{ - post_vsd_en = 0; - post_v_fac = 0x100; - } - - mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST; - val = v_DSP_HACT_END_POST(post_dsp_hact_end) | - v_DSP_HACT_ST_POST(post_dsp_hact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val); - - mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST; - val = v_DSP_VACT_END_POST(post_dsp_vact_end) | - v_DSP_VACT_ST_POST(post_dsp_vact_st); - lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val); - - mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB; - val = v_POST_HS_FACTOR_YRGB(post_h_fac) | - v_POST_VS_FACTOR_YRGB(post_v_fac); - lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val); - - mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN; - val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en); - lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val); - return 0; -} -static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) -{ - int ret = -EINVAL; - int fps; - u16 face = 0; - u32 v=0; - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u16 left_margin = screen->mode.left_margin; - u16 upper_margin = screen->mode.upper_margin; - u16 x_res = screen->mode.xres; - u16 y_res = screen->mode.yres; - u32 mask, val; - u16 h_total,v_total; - - h_total = screen->mode.hsync_len+screen->mode.left_margin + - x_res + screen->mode.right_margin; - v_total = screen->mode.vsync_len+screen->mode.upper_margin + - y_res + screen->mode.lower_margin; - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - switch (screen->face) { - case OUT_P565: - face = OUT_P565; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P666: - face = OUT_P666; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P565: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_D888_P666: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | - m_DITHER_DOWN_SEL; - val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | - v_DITHER_DOWN_SEL(1); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - case OUT_P888: - face = OUT_P888; - mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN; - val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); - break; - default: - dev_err(lcdc_dev->dev, "un supported interface!\n"); - break; - } - switch(screen->type){ - case SCREEN_RGB: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - v = 1 << (3+16); - v |= (!lcdc_dev->id << 3); - break; - case SCREEN_LVDS: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - v = 1 << (3+16); - v |= (!lcdc_dev->id << 3); - break; - case SCREEN_DUAL_LVDS: - mask = m_RGB_OUT_EN; - val = v_RGB_OUT_EN(1); - v = 1 << (3+16); - v |= (!lcdc_dev->id << 3); - break; - case SCREEN_HDMI: - mask = m_HDMI_OUT_EN; - val = v_HDMI_OUT_EN(1); - v = 1 << (4+16); - v |= (!lcdc_dev->id << 4); - break; - case SCREEN_MIPI: - mask = m_MIPI_OUT_EN; - val = v_MIPI_OUT_EN(1); - v = (1 << (6+16))||(1 << (9+16)); - v |= (!lcdc_dev->id << 6); - v |= (!lcdc_dev->id << 9); - break; - case SCREEN_DUAL_MIPI: - mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN; - val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1); - - v = (1 << (6+16))||(1 << (9+16)); - v |= (!lcdc_dev->id << 6); - v |= (!lcdc_dev->id << 9); - break; - case SCREEN_EDP: - mask = m_EDP_OUT_EN; - val = v_EDP_OUT_EN(1); - - v = 1 << (5+16); - v |= (!lcdc_dev->id << 5); - break; - } - lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); - writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); - - mask = m_DSP_OUT_MODE | m_DSP_OUT_MODE | m_DSP_VSYNC_POL | - m_DSP_DEN_POL | m_DSP_DCLK_POL; - val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) | - v_DSP_VSYNC_POL(screen->pin_vsync) | - v_DSP_VSYNC_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_DSP_BG_SWAP | m_DSP_RB_SWAP | - m_DSP_RB_SWAP | m_DSP_DELTA_SWAP | - m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN | - m_DSP_BLACK_EN; - val = v_DSP_BG_SWAP(screen->swap_gb) | - v_DSP_RB_SWAP(screen->swap_rb) | - v_DSP_RG_SWAP(screen->swap_rg) | - v_DSP_DELTA_SWAP(screen->swap_delta) | - v_DSP_DUMMY_SWAP(screen->swap_dumy) | - v_DSP_OUT_ZERO(0) | v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); - - mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED; - val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | - v_DSP_BG_RED(0); - lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val); - - mask = m_DSP_HS_PW | m_DSP_HTOTAL; - val = v_DSP_HS_PW(screen->mode.hsync_len) | - v_DSP_HS_PW(h_total); - lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val); - - mask = m_DSP_HACT_END | m_DSP_HACT_ST; - val = v_DSP_HACT_END(screen->mode.hsync_len + left_margin + x_res) | - v_DSP_HACT_ST(screen->mode.hsync_len + left_margin); - lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val); - - mask = m_DSP_VS_PW | m_DSP_VTOTAL; - val = v_DSP_VS_PW(screen->mode.vsync_len) | - v_DSP_VTOTAL(v_total); - lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val); - - mask = m_DSP_VACT_END | m_DSP_VACT_ST; - val = v_DSP_VACT_END(screen->mode.vsync_len + upper_margin + y_res) | - v_DSP_VACT_ST(screen->mode.vsync_len + upper_margin); - lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val); - - rk3288_lcdc_post_cfg(dev_drv); - } - - //SYS_CTRL RGB_OUT/HDMI_OUT/EDP_OUT/MIPI_OUT EN - spin_unlock(&lcdc_dev->reg_lock); - - ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); - if (ret) - dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); - lcdc_dev->pixclock = - div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - lcdc_dev->driver.pixclock = lcdc_dev->pixclock; - - fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); - screen->ft = 1000 / fps; - dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", - lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); - - if (screen->init) - screen->init(); - - return 0; -} - -/*enable layer,open:1,enable;0 disable*/ -static int win0_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[0]->state = open; - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win1_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[1]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[2]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win3_open(struct lcdc_device *lcdc_dev, bool open) -{ - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - if (open) { - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "wakeup from standby!\n"); - lcdc_dev->standby = 0; - } - lcdc_dev->atv_layer_cnt++; - } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { - lcdc_dev->atv_layer_cnt--; - } - lcdc_dev->driver.win[3]->state = open; - - /*if no layer used,disable lcdc*/ - if (!lcdc_dev->atv_layer_cnt) { - dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); - lcdc_dev->standby = 1; - } - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - - -static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, - bool open) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - - /*enable clk,when first layer open */ - if ((open) && (!lcdc_dev->atv_layer_cnt)) { - rk3288_lcdc_pre_init(dev_drv); - rk3288_lcdc_clk_enable(lcdc_dev); - rk3288_lcdc_reg_restore(lcdc_dev); - rk3288_load_screen(dev_drv, 1); - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) - rk3288_lcdc_set_lut(dev_drv); - spin_unlock(&lcdc_dev->reg_lock); - } - - if (win_id == 0) - win0_open(lcdc_dev, open); - else if (win_id == 1) - win1_open(lcdc_dev, open); - else if (win_id == 2) - win2_open(lcdc_dev, open); - else if (win_id == 3) - win3_open(lcdc_dev, open); - else - dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); - - /*when all layer closed,disable clk */ - if ((!open) && (!lcdc_dev->atv_layer_cnt)) { - rk3288_lcdc_disable_irq(lcdc_dev); - rk3288_lcdc_reg_update(dev_drv); - rk3288_lcdc_clk_disable(lcdc_dev); - } - - return 0; -} - -static int win0_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start+win->area[0].y_offset;//win->smem_start + win->y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n", - lcdc_dev->id, __func__, y_addr, uv_addr); - //printk("y_offset=0x%x,y_addr=0x%x\n",win->area[0].y_offset,y_addr); - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - win->area[0].y_addr = y_addr; - win->area[0].uv_addr = uv_addr; - } - spin_unlock(&lcdc_dev->reg_lock); - - return 0; - -} - -static int win1_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 y_addr; - u32 uv_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - uv_addr = win->area[0].cbr_start + win->area[0].c_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n", - lcdc_dev->id, __func__, y_addr, uv_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) - win->area[0].y_addr = y_addr; - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int win2_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 i,y_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", - lcdc_dev->id, __func__, y_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) - for(i=0;iarea_num;i++){ - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win3_display(struct lcdc_device *lcdc_dev, - struct rk_lcdc_win *win) -{ - u32 i,y_addr; - y_addr = win->area[0].smem_start + win->area[0].y_offset; - DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", - lcdc_dev->id, __func__, y_addr); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) - for(i=0;iarea_num;i++){ - win->area[i].y_addr = - win->area[i].smem_start + win->area[i].y_offset; - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - - -static int rk3288_lcdc_win_display(struct rk_lcdc_driver *dev_drv, struct rk_lcdc_win *win,int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u32 mask, val; - - lcdc_dev->atv_layer_cnt = dev_drv->atv_layer_cnt; - if(!screen){ - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - //overlay - if(win_id == 0){ - win0_display(lcdc_dev, win); - }else if(win_id == 1){ - win1_display(lcdc_dev, win); - }else if(win_id == 2){ - win2_display(lcdc_dev, win); - }else if(win_id == 3){ - win3_display(lcdc_dev, win); - }else{ - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - /*this is the first frame of the system ,enable frame start interrupt */ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR | - m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR | - m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM; - val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) | - v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) | - v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin + - screen->mode.yres -1); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - lcdc_cfg_done(lcdc_dev); - - } - return 0; -} - -static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - u32 mask, val; -#if defined(WAIT_FOR_SYNC) - int timeout; - unsigned long flags; -#endif - //printk("rk3288_lcdc_pan_display,win_num=%d\n",dev_drv->atv_layer_cnt); - lcdc_dev->atv_layer_cnt = dev_drv->atv_layer_cnt; - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - //overlay - if(win_id == 0){ - win0_display(lcdc_dev, win); - }else if(win_id == 1){ - win1_display(lcdc_dev, win); - }else if(win_id == 2){ - win2_display(lcdc_dev, win); - }else if(win_id == 3){ - win3_display(lcdc_dev, win); - }else{ - dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); - return -EINVAL; - } - - - - /*this is the first frame of the system ,enable frame start interrupt */ - if ((dev_drv->first_frame)) { - dev_drv->first_frame = 0; - mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR | - m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR | - m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM; - val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) | - v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) | - v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin + - screen->mode.yres -1); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); - lcdc_cfg_done(lcdc_dev); - } -#if defined(WAIT_FOR_SYNC) - spin_lock_irqsave(&dev_drv->cpl_lock, flags); - init_completion(&dev_drv->frame_done); - spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); - timeout = wait_for_completion_timeout(&dev_drv->frame_done, - msecs_to_jiffies(dev_drv-> - cur_screen->ft + - 5)); - if (!timeout && (!dev_drv->frame_done.done)) { - dev_info(dev_drv->dev, "wait for new frame start time out!\n"); - return -ETIMEDOUT; - } -#endif - //printk("rk3288_lcdc_pan_display,win_num=%d\n",dev_drv->atv_layer_cnt); - dev_drv->ops->ovl_mgr(dev_drv, 0, 1); - rk3288_lcdc_reg_update(dev_drv); - - return 0; -} - -static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win) -{ - u16 srcW; - u16 srcH; - u16 dstW; - u16 dstH; - u16 yrgb_srcW; - u16 yrgb_srcH; - u16 yrgb_dstW; - u16 yrgb_dstH; - u32 yrgb_vScaleDnMult; - u32 yrgb_xscl_factor; - u32 yrgb_yscl_factor; - u8 yrgb_vsd_bil_gt2=0; - u8 yrgb_vsd_bil_gt4=0; - - u16 cbcr_srcW; - u16 cbcr_srcH; - u16 cbcr_dstW; - u16 cbcr_dstH; - u32 cbcr_vScaleDnMult; - u32 cbcr_xscl_factor; - u32 cbcr_yscl_factor; - u8 cbcr_vsd_bil_gt2=0; - u8 cbcr_vsd_bil_gt4=0; - - - srcW = win->area[0].xact; - srcH = win->area[0].yact; - dstW = win->area[0].xsize; - dstH = win->area[0].ysize; - - //yrgb scl mode - yrgb_srcW = srcW; - yrgb_srcH = srcH; - yrgb_dstW = dstW; - yrgb_dstH = dstH; - if(yrgb_srcW < yrgb_dstW){ - win->yrgb_hor_scl_mode = SCALE_UP; - }else if(yrgb_srcW > yrgb_dstW){ - win->yrgb_hor_scl_mode = SCALE_DOWN; - }else{ - win->yrgb_hor_scl_mode = SCALE_NONE; - } - - if(yrgb_srcH < yrgb_dstH){ - win->yrgb_ver_scl_mode = SCALE_UP; - }else if (yrgb_srcH > yrgb_dstH){ - win->yrgb_ver_scl_mode = SCALE_DOWN; - }else{ - win->yrgb_ver_scl_mode = SCALE_NONE; - } - - //cbcr scl mode - switch (win->format) { - case YUV422: - cbcr_srcW = srcW/2; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - break; - case YUV420: - cbcr_srcW = srcW/2; - cbcr_dstW = dstW; - cbcr_srcH = srcH/2; - cbcr_dstH = dstH; - break; - case YUV444: - cbcr_srcW = srcW; - cbcr_dstW = dstW; - cbcr_srcH = srcH; - cbcr_dstH = dstH; - break; - default: - cbcr_srcW = 0; - cbcr_dstW = 0; - cbcr_srcH = 0; - cbcr_dstH = 0; - break; - } - if(cbcr_srcW < cbcr_dstW){ - win->cbr_hor_scl_mode = SCALE_UP; - }else if(cbcr_srcW > cbcr_dstW){ - win->cbr_hor_scl_mode = SCALE_DOWN; - }else{ - win->cbr_hor_scl_mode = SCALE_NONE; - } - - if(cbcr_srcH < cbcr_dstH){ - win->cbr_ver_scl_mode = SCALE_UP; - }else if(cbcr_srcH > cbcr_dstH){ - win->cbr_ver_scl_mode = SCALE_DOWN; - }else{ - win->cbr_ver_scl_mode = SCALE_NONE; - } - DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n" - "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" - "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" - ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW, - yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode, - cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH, - win->cbr_hor_scl_mode,win->cbr_ver_scl_mode); - - //line buffer mode - if((win->format == YUV422) || (win->format == YUV420)){ - if(win->cbr_hor_scl_mode == SCALE_DOWN){ - if(cbcr_dstW > 3840){ - printk("ERROR cbcr_dst_width exceeds 3840\n"); - }else if(cbcr_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(cbcr_dstW > 1920){ - if(win->yrgb_hor_scl_mode == SCALE_DOWN){ - if(yrgb_dstW > 3840){ - printk("ERROR yrgb_dst_width exceeds 3840\n"); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else{ - printk("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); - } - } - }else if(cbcr_dstW > 1280){ - win->win_lb_mode = LB_YUV_3840X5; - }else{ - win->win_lb_mode = LB_YUV_2560X8; - } - } else { //SCALE_UP or SCALE_NONE - if(cbcr_srcW > 3840){ - printk("ERROR cbcr_act_width exceeds 3840\n"); - }else if(cbcr_srcW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(cbcr_srcW > 1920){ - if(win->yrgb_hor_scl_mode == SCALE_DOWN){ - if(yrgb_dstW > 3840){ - printk("ERROR yrgb_dst_width exceeds 3840\n"); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else{ - printk("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); - } - } - }else if(cbcr_srcW > 1280){ - win->win_lb_mode = LB_YUV_3840X5; - }else{ - win->win_lb_mode = LB_YUV_2560X8; - } - } - }else { - if(win->yrgb_hor_scl_mode == SCALE_DOWN){ - if(yrgb_dstW > 3840){ - printk("ERROR yrgb_dsp_width exceeds 3840\n"); - }else if(yrgb_dstW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_dstW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else if(yrgb_dstW > 1280){ - win->win_lb_mode = LB_RGB_1920X5; - }else{ - win->win_lb_mode = LB_RGB_1280X8; - } - }else{ //SCALE_UP or SCALE_NONE - if(yrgb_srcW > 3840){ - printk("ERROR yrgb_act_width exceeds 3840\n"); - }else if(yrgb_srcW > 2560){ - win->win_lb_mode = LB_RGB_3840X2; - }else if(yrgb_srcW > 1920){ - win->win_lb_mode = LB_RGB_2560X4; - }else if(yrgb_srcW > 1280){ - win->win_lb_mode = LB_RGB_1920X5; - }else{ - win->win_lb_mode = LB_RGB_1280X8; - } - } - } - DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode); - - //vsd/vsu scale ALGORITHM - - win->yrgb_hsd_mode = SCALE_DOWN_BIL;//not to specify - win->cbr_hsd_mode = SCALE_DOWN_BIL;//not to specify - win->yrgb_vsd_mode = SCALE_DOWN_BIL;//not to specify - win->cbr_vsd_mode = SCALE_DOWN_BIL;//not to specify - switch(win->win_lb_mode){ - case LB_YUV_3840X5: - case LB_YUV_2560X8: - case LB_RGB_1920X5: - case LB_RGB_1280X8: - win->yrgb_vsu_mode = SCALE_UP_BIC; - win->cbr_vsu_mode = SCALE_UP_BIC; - break; - case LB_RGB_3840X2: - if(win->yrgb_ver_scl_mode != SCALE_NONE) { - printk("ERROR : not allow yrgb ver scale\n"); - } - if(win->cbr_ver_scl_mode != SCALE_NONE) { - printk("ERROR : not allow cbcr ver scale\n"); - } - break; - case LB_RGB_2560X4: - win->yrgb_vsu_mode = SCALE_UP_BIL; - win->cbr_vsu_mode = SCALE_UP_BIL; - break; - default: - break; - } - DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n", - win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode, - win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode); - - //SCALE FACTOR - - //(1.1)YRGB HOR SCALE FACTOR - switch(win->yrgb_hor_scl_mode){ - case SCALE_NONE: - yrgb_xscl_factor = (1<yrgb_hsd_mode) - { - case SCALE_DOWN_BIL: - yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW); - break; - case SCALE_DOWN_AVG: - yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW); - break; - default : - break; - } - break; - default : - break; - } //win->yrgb_hor_scl_mode - - //(1.2)YRGB VER SCALE FACTOR - switch(win->yrgb_ver_scl_mode) - { - case SCALE_NONE: - yrgb_yscl_factor = (1<yrgb_vsu_mode) - { - case SCALE_UP_BIL: - yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH); - break; - case SCALE_UP_BIC: - if(yrgb_srcH < 3){ - printk("yrgb_srcH should be greater than 3 !!!\n"); - } - yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH); - break; - default : - break; - } - break; - case SCALE_DOWN: - switch(win->yrgb_vsd_mode) - { - case SCALE_DOWN_BIL: - yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH); - yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult); - if(yrgb_vScaleDnMult == 4){ - yrgb_vsd_bil_gt4 = 1; - yrgb_vsd_bil_gt2 = 0; - }else if(yrgb_vScaleDnMult == 2){ - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 1; - }else{ - yrgb_vsd_bil_gt4 = 0; - yrgb_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH); - break; - default: - break; - } //win->yrgb_vsd_mode - break; - default : - break; - } - win->scale_yrgb_x = yrgb_xscl_factor; - win->scale_yrgb_y = yrgb_yscl_factor; - win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4; - win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2; - DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor, - yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2); - - //(2.1)CBCR HOR SCALE FACTOR - switch(win->cbr_hor_scl_mode) - { - case SCALE_NONE: - cbcr_xscl_factor = (1<cbr_hsd_mode) - { - case SCALE_DOWN_BIL: - cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW); - break; - case SCALE_DOWN_AVG: - cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW); - break; - default : - break; - } - break; - default : - break; - } //win->cbr_hor_scl_mode - - //(2.2)CBCR VER SCALE FACTOR - switch(win->cbr_ver_scl_mode) - { - case SCALE_NONE: - cbcr_yscl_factor = (1<cbr_vsu_mode) - { - case SCALE_UP_BIL: - cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH); - break; - case SCALE_UP_BIC: - if(cbcr_srcH < 3) { - printk("[hxx_dbg] cbcr_srcH should be greater than 3 !!!\n"); - } - cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH); - break; - default : - break; - } - break; - case SCALE_DOWN: - switch(win->cbr_vsd_mode) - { - case SCALE_DOWN_BIL: - cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH); - cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult); - if(cbcr_vScaleDnMult == 4){ - cbcr_vsd_bil_gt4 = 1; - cbcr_vsd_bil_gt2 = 0; - }else if(cbcr_vScaleDnMult == 2){ - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 1; - }else{ - cbcr_vsd_bil_gt4 = 0; - cbcr_vsd_bil_gt2 = 0; - } - break; - case SCALE_DOWN_AVG: - cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH); - break; - default : - break; - } - break; - default : - break; - } - win->scale_cbcr_x = cbcr_xscl_factor; - win->scale_cbcr_y = cbcr_yscl_factor; - win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4; - win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2; - - DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor, - cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2); - return 0; -} - - - -static int win0_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact,yact,xvir, yvir,xpos, ypos; - u8 fmt_cfg = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - rk3288_lcdc_cal_scl_fac(win);//fac,lb.gt2,gt4 - switch (win->format){ - case ARGB888: - fmt_cfg = 0; - win->swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - win->swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - win->swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - win->swap_rb = 0; - break; - case YUV422: - fmt_cfg = 5; - win->swap_rb = 0; - break; - case YUV420: - fmt_cfg = 4; - win->swap_rb = 0; - break; - case YUV444: - fmt_cfg = 6; - win->swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - win->fmt_cfg = fmt_cfg; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].xvir; - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->format, fmt), xact, - yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; - -} - -static int win1_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - u32 xact,yact,xvir, yvir,xpos, ypos; - u8 fmt_cfg = 0; - char fmt[9] = "NULL"; - - xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; - ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - rk3288_lcdc_cal_scl_fac(win);//fac,lb.gt2,gt4 - switch (win->format){ - case ARGB888: - fmt_cfg = 0; - win->swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - win->swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - win->swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - win->swap_rb = 0; - break; - case YUV422: - fmt_cfg = 5; - win->swap_rb = 0; - break; - case YUV420: - fmt_cfg = 4; - win->swap_rb = 0; - break; - case YUV444: - fmt_cfg = 6; - win->swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", - __func__); - break; - } - win->fmt_cfg = fmt_cfg; - win->area[0].dsp_stx = xpos; - win->area[0].dsp_sty = ypos; - xact = win->area[0].xact; - yact = win->area[0].yact; - xvir = win->area[0].xvir; - yvir = win->area[0].xvir; - } - spin_unlock(&lcdc_dev->reg_lock); - - DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" - ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, - __func__, get_format_string(win->format, fmt), xact, - yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); - return 0; - -} - -static int win2_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) -{ - int i; - u8 fmt_cfg; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - for(i=0;iarea_num;i++){ - switch (win->format){ - case ARGB888: - fmt_cfg = 0; - win->swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - win->swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - win->swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - win->swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - break; - } - win->fmt_cfg = fmt_cfg; - win->area[i].dsp_stx = win->area[i].xpos + - screen->mode.left_margin + - screen->mode.hsync_len; - win->area[i].dsp_sty = win->area[i].ypos + - screen->mode.upper_margin + - screen->mode.vsync_len;; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - -static int win3_set_par(struct lcdc_device *lcdc_dev, - struct rk_screen *screen, struct rk_lcdc_win *win) - -{ - int i; - u8 fmt_cfg; - - spin_lock(&lcdc_dev->reg_lock); - if(likely(lcdc_dev->clk_on)){ - for(i=0;iarea_num;i++){ - switch (win->format){ - case ARGB888: - fmt_cfg = 0; - win->swap_rb = 0; - break; - case XBGR888: - case ABGR888: - fmt_cfg = 0; - win->swap_rb = 1; - break; - case RGB888: - fmt_cfg = 1; - win->swap_rb = 0; - break; - case RGB565: - fmt_cfg = 2; - win->swap_rb = 0; - break; - default: - dev_err(lcdc_dev->driver.dev, - "%s:un supported format!\n", - __func__); - break; - } - win->fmt_cfg = fmt_cfg; - win->area[i].dsp_stx = win->area[i].xpos + - screen->mode.left_margin + - screen->mode.hsync_len; - win->area[i].dsp_sty = win->area[i].ypos + - screen->mode.upper_margin + - screen->mode.vsync_len;; - } - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; - - -} - -static int rk3288_set_win_par(struct rk_lcdc_driver *dev_drv, - struct rk_screen *screen, struct rk_lcdc_win *win,int win_id) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - switch(win_id) - { - case 0: - win0_set_par(lcdc_dev, screen, win); - break; - case 1: - win1_set_par(lcdc_dev, screen, win); - break; - case 2: - win2_set_par(lcdc_dev, screen, win); - break; - case 3: - win3_set_par(lcdc_dev, screen, win); - break; - default: - dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id); - break; - } - return 0; -} -static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id) -{ - struct rk_lcdc_win *win = NULL; - struct rk_screen *screen = dev_drv->cur_screen; - int i; - - if (!screen) { - dev_err(dev_drv->dev, "screen is null!\n"); - return -ENOENT; - } - for(i=0;ilcdc_win_num;i++){ - if(dev_drv->win[i]->state == 1){ - win = dev_drv->win[i]; - rk3288_set_win_par(dev_drv,screen,win,i); - rk3288_lcdc_win_display(dev_drv,win,i); - } - } - - dev_drv->ops->ovl_mgr(dev_drv, 0, 1); - rk3288_lcdc_reg_update(dev_drv); - - - return 0; -} - -static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, - unsigned long arg, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - u32 panel_size[2]; - void __user *argp = (void __user *)arg; - struct color_key_cfg clr_key_cfg; - - switch (cmd) { - case RK_FBIOGET_PANEL_SIZE: - panel_size[0] = lcdc_dev->screen->mode.xres; - panel_size[1] = lcdc_dev->screen->mode.yres; - if (copy_to_user(argp, panel_size, 8)) - return -EFAULT; - break; - case RK_FBIOPUT_COLOR_KEY_CFG: - if (copy_from_user(&clr_key_cfg, argp, - sizeof(struct color_key_cfg))) - return -EFAULT; - rk3288_lcdc_clr_key_cfg(dev_drv); - lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, - clr_key_cfg.win0_color_key_cfg); - lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, - clr_key_cfg.win1_color_key_cfg); - break; - - default: - break; - } - return 0; -} - -static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) -{ -#if 1 - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - if (dev_drv->screen0->standby) - dev_drv->screen0->standby(1); - if (dev_drv->screen_ctr_info->io_disable) - dev_drv->screen_ctr_info->io_disable(); - dev_drv->suspend_flag = 1; - flush_kthread_worker(&dev_drv->update_regs_worker); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - rk3288_lcdc_disable_irq(lcdc_dev); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(1)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(1)); - lcdc_cfg_done(lcdc_dev); - spin_unlock(&lcdc_dev->reg_lock); - } else { - spin_unlock(&lcdc_dev->reg_lock); - return 0; - } - rk3288_lcdc_clk_disable(lcdc_dev); -#endif - return 0; -} - -static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) -{ -#if 1 - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int i = 0; - int __iomem *c; - int v; - - if (dev_drv->screen_ctr_info->io_enable) - dev_drv->screen_ctr_info->io_enable(); - dev_drv->suspend_flag = 0; - - if (lcdc_dev->atv_layer_cnt) { - rk3288_lcdc_clk_enable(lcdc_dev); - rk3288_lcdc_reg_restore(lcdc_dev); - - spin_lock(&lcdc_dev->reg_lock); - if (dev_drv->cur_screen->dsp_lut) { - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - mdelay(25); - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, - v_DSP_LUT_EN(1)); - } - - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, - v_DSP_OUT_ZERO(0)); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, - v_STANDBY_EN(0)); - lcdc_cfg_done(lcdc_dev); - - spin_unlock(&lcdc_dev->reg_lock); - } - - if (dev_drv->screen0->standby) - dev_drv->screen0->standby(0); -#endif - return 0; -} - -static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv, - int win_id, int blank_mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - spin_lock(&lcdc_dev->reg_lock); - if (likely(lcdc_dev->clk_on)) { - switch (blank_mode) { - case FB_BLANK_UNBLANK: - rk3288_lcdc_early_resume(dev_drv); - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(0)); - break; - case FB_BLANK_NORMAL: - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(1)); - rk3288_lcdc_early_suspend(dev_drv); - break; - default: - lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, - v_DSP_BLANK_EN(1)); - rk3288_lcdc_early_suspend(dev_drv); - break; - } - lcdc_cfg_done(lcdc_dev); - - } - spin_unlock(&lcdc_dev->reg_lock); - - dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); - - return 0; -} - -static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id) -{ - return 0; -} - -//overlay will be do at regupdate -static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl; - unsigned int mask, val; - int win0_order,win1_order,win2_order,win3_order; - win0_order = dev_drv->win[0]->z_order; - win1_order = dev_drv->win[1]->z_order; - win2_order = dev_drv->win[2]->z_order; - win3_order = dev_drv->win[3]->z_order; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on){ - if(set){ - mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL | - m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL; - val = v_DSP_LAYER0_SEL(win0_order) | - v_DSP_LAYER1_SEL(win1_order) | - v_DSP_LAYER2_SEL(win2_order) | - v_DSP_LAYER3_SEL(win3_order); - lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val); - }else{ - win0_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL); - win1_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL); - win2_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL); - win3_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL); - ovl = win3_order*1000 + win2_order*100 + win1_order *10 + win0_order; - } - }else{ - ovl = -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - - return ovl; -} - -static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, - char *buf, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct - lcdc_device, - driver); - u32 fmt_id; - char format_w0[9] = "NULL"; - char format_w1[9] = "NULL"; - char format_w2[9] = "NULL"; - char format_w3[9] = "NULL"; - u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor; - u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel; - u8 w0_state,w1_state,w2_state,w3_state; - u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state; - u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state; - - u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x,w0_st_y; - u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x,w1_st_y; - u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac; - u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac; - - u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y; - u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x; - u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y; - u32 w2_0_st_x,w2_1_st_x,w2_2_st_x,w2_3_st_x; - u32 w2_0_st_y,w2_1_st_y,w2_2_st_y,w2_3_st_y; - - u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y; - u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x; - u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y; - u32 w3_0_st_x,w3_1_st_x,w3_2_st_x,w3_3_st_x; - u32 w3_0_st_y,w3_1_st_y,w3_2_st_y,w3_3_st_y; - - spin_lock(&lcdc_dev->reg_lock); - - - if (lcdc_dev->clk_on) { - zorder = lcdc_readl(lcdc_dev, DSP_CTRL1); - layer0_sel = zorder | m_DSP_LAYER0_SEL; - layer1_sel = zorder | m_DSP_LAYER1_SEL; - layer2_sel = zorder | m_DSP_LAYER2_SEL; - layer3_sel = zorder | m_DSP_LAYER3_SEL; - //WIN0 - win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); - w0_state = win_ctrl | m_WIN0_EN; - fmt_id = win_ctrl | m_WIN0_DATA_FMT; - switch (fmt_id) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w0, "YCbCr420"); - break; - case 5: - strcpy(format_w0, "YCbCr422"); - break; - case 6: - strcpy(format_w0, "YCbCr444"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - vir_info = lcdc_readl(lcdc_dev,WIN0_VIR); - act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST); - y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR); - w0_vir_y = vir_info | m_WIN0_VIR_STRIDE; - w0_vir_uv = vir_info | m_WIN0_VIR_STRIDE_UV; - w0_act_x = act_info | m_WIN0_ACT_WIDTH; - w0_act_y = act_info | m_WIN0_ACT_HEIGHT; - w0_dsp_x = dsp_info | m_WIN0_DSP_WIDTH; - w0_dsp_y = dsp_info | m_WIN0_DSP_HEIGHT; - w0_st_x = dsp_st | m_WIN0_DSP_XST; - w0_st_y = dsp_st | m_WIN0_DSP_YST; - w0_y_h_fac = y_factor | m_WIN0_HS_FACTOR_YRGB; - w0_y_v_fac = y_factor | m_WIN0_VS_FACTOR_YRGB; - w0_uv_h_fac = uv_factor | m_WIN0_HS_FACTOR_CBR; - w0_uv_v_fac = uv_factor | m_WIN0_VS_FACTOR_CBR; - - //WIN1 - win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); - w1_state = win_ctrl | m_WIN1_EN; - fmt_id = win_ctrl | m_WIN1_DATA_FMT; - switch (fmt_id) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w0, "YCbCr420"); - break; - case 5: - strcpy(format_w0, "YCbCr422"); - break; - case 6: - strcpy(format_w0, "YCbCr444"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - vir_info = lcdc_readl(lcdc_dev,WIN1_VIR); - act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO); - dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO); - dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST); - y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB); - uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR); - w1_vir_y = vir_info | m_WIN1_VIR_STRIDE; - w1_vir_uv = vir_info | m_WIN1_VIR_STRIDE_UV; - w1_act_x = act_info | m_WIN1_ACT_WIDTH; - w1_act_y = act_info | m_WIN1_ACT_HEIGHT; - w1_dsp_x = dsp_info | m_WIN1_DSP_WIDTH; - w1_dsp_y = dsp_info | m_WIN1_DSP_HEIGHT; - w1_st_x = dsp_st | m_WIN1_DSP_XST; - w1_st_y = dsp_st | m_WIN1_DSP_YST; - w1_y_h_fac = y_factor | m_WIN1_HS_FACTOR_YRGB; - w1_y_v_fac = y_factor | m_WIN1_VS_FACTOR_YRGB; - w1_uv_h_fac = uv_factor | m_WIN1_HS_FACTOR_CBR; - w1_uv_v_fac = uv_factor | m_WIN1_VS_FACTOR_CBR; - //WIN2 - win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); - w2_state = win_ctrl | m_WIN2_EN; - w2_0_state = win_ctrl | m_WIN2_MST0_EN; - w2_1_state = win_ctrl | m_WIN2_MST1_EN; - w2_2_state = win_ctrl | m_WIN2_MST2_EN; - w2_3_state = win_ctrl | m_WIN2_MST3_EN; - vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1); - w2_0_vir_y = vir_info | m_WIN2_VIR_STRIDE0; - w2_1_vir_y = vir_info | m_WIN2_VIR_STRIDE1; - vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3); - w2_2_vir_y = vir_info | m_WIN2_VIR_STRIDE2; - w2_3_vir_y = vir_info | m_WIN2_VIR_STRIDE3; - fmt_id = win_ctrl | m_WIN2_DATA_FMT; - switch (fmt_id) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w1,"8bpp"); - break; - case 5: - strcpy(format_w1,"4bpp"); - break; - case 6: - strcpy(format_w1,"2bpp"); - break; - case 7: - strcpy(format_w1,"1bpp"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0); - w2_0_dsp_x = dsp_info | m_WIN2_DSP_WIDTH0; - w2_0_dsp_y = dsp_info | m_WIN2_DSP_HEIGHT0; - w2_0_st_x = dsp_st | m_WIN2_DSP_XST0; - w2_0_st_y = dsp_st | m_WIN2_DSP_YST0; - - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1); - w2_1_dsp_x = dsp_info | m_WIN2_DSP_WIDTH1; - w2_1_dsp_y = dsp_info | m_WIN2_DSP_HEIGHT1; - w2_1_st_x = dsp_st | m_WIN2_DSP_XST1; - w2_1_st_y = dsp_st | m_WIN2_DSP_YST1; - - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2); - w2_2_dsp_x = dsp_info | m_WIN2_DSP_WIDTH2; - w2_2_dsp_y = dsp_info | m_WIN2_DSP_HEIGHT2; - w2_2_st_x = dsp_st | m_WIN2_DSP_XST2; - w2_2_st_y = dsp_st | m_WIN2_DSP_YST2; - - dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3); - w2_3_dsp_x = dsp_info | m_WIN2_DSP_WIDTH3; - w2_3_dsp_y = dsp_info | m_WIN2_DSP_HEIGHT3; - w2_3_st_x = dsp_st | m_WIN2_DSP_XST3; - w2_3_st_y = dsp_st | m_WIN2_DSP_YST3; - - //WIN3 - win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); - w3_state = win_ctrl | m_WIN3_EN; - w3_0_state = win_ctrl | m_WIN3_MST0_EN; - w3_1_state = win_ctrl | m_WIN3_MST1_EN; - w3_2_state = win_ctrl | m_WIN3_MST2_EN; - w3_3_state = win_ctrl | m_WIN3_MST3_EN; - vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1); - w3_0_vir_y = vir_info | m_WIN3_VIR_STRIDE0; - w3_1_vir_y = vir_info | m_WIN3_VIR_STRIDE1; - vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3); - w3_2_vir_y = vir_info | m_WIN3_VIR_STRIDE2; - w3_3_vir_y = vir_info | m_WIN3_VIR_STRIDE3; - fmt_id = win_ctrl | m_WIN3_DATA_FMT; - switch (fmt_id) { - case 0: - strcpy(format_w0, "ARGB888"); - break; - case 1: - strcpy(format_w0, "RGB888"); - break; - case 2: - strcpy(format_w0, "RGB565"); - break; - case 4: - strcpy(format_w1,"8bpp"); - break; - case 5: - strcpy(format_w1,"4bpp"); - break; - case 6: - strcpy(format_w1,"2bpp"); - break; - case 7: - strcpy(format_w1,"1bpp"); - break; - default: - strcpy(format_w0, "invalid\n"); - break; - } - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0); - w3_0_dsp_x = dsp_info | m_WIN3_DSP_WIDTH0; - w3_0_dsp_y = dsp_info | m_WIN3_DSP_HEIGHT0; - w3_0_st_x = dsp_st | m_WIN3_DSP_XST0; - w3_0_st_y = dsp_st | m_WIN3_DSP_YST0; - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1); - w3_1_dsp_x = dsp_info | m_WIN3_DSP_WIDTH1; - w3_1_dsp_y = dsp_info | m_WIN3_DSP_HEIGHT1; - w3_1_st_x = dsp_st | m_WIN3_DSP_XST1; - w3_1_st_y = dsp_st | m_WIN3_DSP_YST1; - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2); - w3_2_dsp_x = dsp_info | m_WIN3_DSP_WIDTH2; - w3_2_dsp_y = dsp_info | m_WIN3_DSP_HEIGHT2; - w3_2_st_x = dsp_st | m_WIN3_DSP_XST2; - w3_2_st_y = dsp_st | m_WIN3_DSP_YST2; - - dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3); - dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3); - w3_3_dsp_x = dsp_info | m_WIN3_DSP_WIDTH3; - w3_3_dsp_y = dsp_info | m_WIN3_DSP_HEIGHT3; - w3_3_st_x = dsp_st | m_WIN3_DSP_XST3; - w3_3_st_y = dsp_st | m_WIN3_DSP_YST3; - - } else { - spin_unlock(&lcdc_dev->reg_lock); - return -EPERM; - } - spin_unlock(&lcdc_dev->reg_lock); - return snprintf(buf, PAGE_SIZE, - "z-order:" - " layer0_sel:win[%d]\n" - " layer1_sel:win[%d]\n" - " layer2_sel:win[%d]\n" - " layer3_sel:win[%d]\n" - "win0:\n" - " state:%d\n" - " fmt:%s\n" - " y_vir:%d\n" - " uv_vir:%d\n" - " xact:%d\n" - " yact:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " y_h_fac:%d\n" - " y_v_fac:%d\n" - " uv_h_fac:%d\n" - " uv_v_fac:%d\n" - " y_addr: 0x%x\n" - " uv_addr:0x%x\n" - "win1:\n" - " state:%d\n" - " fmt:%s\n" - " y_vir:%d\n" - " uv_vir:%d\n" - " xact:%d\n" - " yact:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " y_h_fac:%d\n" - " y_v_fac:%d\n" - " uv_h_fac:%d\n" - " uv_v_fac:%d\n" - " y_addr: 0x%x\n" - " uv_addr:0x%x\n" - "win2:\n" - " state:%d\n" - " fmt:%s\n" - " area0:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - " area1:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - " area2:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - " area3:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - "win3:\n" - " state:%d\n" - " fmt:%s\n" - " area0:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - " area1:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " area2:\n" - " addr:0x%x\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n" - " area3:\n" - " state:%d\n" - " y_vir:%d\n" - " dsp_x:%d\n" - " dsp_y:%d\n" - " x_st:%d\n" - " y_st:%d\n" - " addr:0x%x\n", - layer0_sel,layer1_sel,layer2_sel,layer3_sel, - w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y, - w0_dsp_x,w0_dsp_y,w0_st_x,w0_st_y,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac, - w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST), - lcdc_readl(lcdc_dev, WIN0_CBR_MST), - - w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y, - w1_dsp_x,w1_dsp_y,w1_st_x,w1_st_y,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac, - w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST), - lcdc_readl(lcdc_dev, WIN1_CBR_MST), - - w2_state,format_w2, - w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y, - w2_0_st_x,w2_0_st_y,lcdc_readl(lcdc_dev, WIN2_MST0), - - w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y, - w2_1_st_x,w2_1_st_y,lcdc_readl(lcdc_dev, WIN2_MST1), - - w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y, - w2_2_st_x,w2_2_st_y,lcdc_readl(lcdc_dev, WIN2_MST2), - - w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y, - w2_3_st_x,w2_3_st_y,lcdc_readl(lcdc_dev, WIN2_MST3), - - w3_state,format_w3, - w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y, - w3_0_st_x,w3_0_st_y,lcdc_readl(lcdc_dev, WIN3_MST0), - - w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y, - w3_1_st_x,w3_1_st_y,lcdc_readl(lcdc_dev, WIN3_MST1), - - w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y, - w3_2_st_x,w3_2_st_y,lcdc_readl(lcdc_dev, WIN3_MST2), - - w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y, - w3_3_st_x,w3_3_st_y,lcdc_readl(lcdc_dev, WIN3_MST3) - ); - -} - -static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, - bool set) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - u64 ft = 0; - u32 dotclk; - int ret; - u32 pixclock; - u32 x_total, y_total; - if (set) { - ft = div_u64(1000000000000llu, fps); - x_total = - screen->mode.upper_margin + screen->mode.lower_margin + - screen->mode.yres + screen->mode.vsync_len; - y_total = - screen->mode.left_margin + screen->mode.right_margin + - screen->mode.xres + screen->mode.hsync_len; - dev_drv->pixclock = div_u64(ft, x_total * y_total); - dotclk = div_u64(1000000000000llu, dev_drv->pixclock); - ret = clk_set_rate(lcdc_dev->dclk, dotclk); - } - - pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); - dev_drv->pixclock = lcdc_dev->pixclock = pixclock; - fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); - screen->ft = 1000 / fps; /*one frame time in ms */ - - if (set) - dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, - clk_get_rate(lcdc_dev->dclk), fps); - - return fps; -} - -static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, - enum fb_win_map_order order) -{ - mutex_lock(&dev_drv->fb_win_id_mutex); - if (order == FB_DEFAULT_ORDER) - order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3; - dev_drv->fb3_win_id = order / 1000; - dev_drv->fb2_win_id = (order / 100) % 10; - dev_drv->fb1_win_id = (order / 10) % 10; - dev_drv->fb0_win_id = order % 10; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return 0; -} - -static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, - const char *id) -{ - int win_id = 0; - mutex_lock(&dev_drv->fb_win_id_mutex); - if (!strcmp(id, "fb0") || !strcmp(id, "fb4")) - win_id = dev_drv->fb0_win_id; - else if (!strcmp(id, "fb1") || !strcmp(id, "fb5")) - win_id = dev_drv->fb1_win_id; - else if (!strcmp(id, "fb2") || !strcmp(id, "fb6")) - win_id = dev_drv->fb2_win_id; - else if (!strcmp(id, "fb3") || !strcmp(id, "fb7")) - win_id = dev_drv->fb3_win_id; - mutex_unlock(&dev_drv->fb_win_id_mutex); - - return win_id; -} - -static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut) -{ - int i = 0; - int __iomem *c; - int v; - int ret = 0; - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); - lcdc_cfg_done(lcdc_dev); - msleep(25); - if (dev_drv->cur_screen->dsp_lut) { - for (i = 0; i < 256; i++) { - v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; - c = lcdc_dev->dsp_lut_addr_base + i; - writel_relaxed(v, c); - - } - } else { - dev_err(dev_drv->dev, "no buffer to backup lut data!\n"); - ret = -1; - } - lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); - lcdc_cfg_done(lcdc_dev); - - return ret; -} - -static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN, - v_DIRECT_PATH_EN(open)); - lcdc_cfg_done(lcdc_dev); - return 0; -} - -static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) -{ - struct lcdc_device *lcdc_dev = container_of(dev_drv, - struct lcdc_device, driver); - lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL, - v_DIRECT_PATCH_SEL(win_id)); - lcdc_cfg_done(lcdc_dev); - return 0; - -} - -static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN); - return ovl; -} - -int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 int_reg; - int ret; - - if (lcdc_dev->clk_on) { - int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); - if (int_reg & m_LINE_FLAG_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, - v_LINE_FLAG_INTR_CLR(1)); - ret = RK_LF_STATUS_FC; - } else - ret = RK_LF_STATUS_FR; - } else { - ret = RK_LF_STATUS_NC; - } - - return ret; -} -static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,unsigned int *dsp_addr) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - - if(lcdc_dev->clk_on){ - dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); - dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST); - } - return 0; -} - -static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,int mode) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - struct rk_screen *screen = dev_drv->cur_screen; - int total_pixel,calc_pixel,stage_up,stage_down; - u32 mask, val; - - u32 cabc_mode[5][3]={ - //num ,up, down - {2, 10, 10}, //mode 1 - {4, 10, 10}, //mode 2 - {6, 10, 10}, //mode 3 - {8, 10, 10}, //mode 4 - {10, 10, 10}, //mode 5 - }; - if(mode == 0){ - printk("close cabc\n"); - mask = m_CABC_EN; - val = v_CABC_EN(0); - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); - return 0; - } - - total_pixel = screen->mode.xres * screen->mode.yres; - calc_pixel = total_pixel * (100 - cabc_mode[mode-1][0])*100; - stage_up = cabc_mode[mode-1][1]; - stage_down = cabc_mode[mode-1][2]; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on){ - mask = m_CABC_TOTAL_NUM | m_CABC_TOTAL_NUM; - val = v_CABC_TOTAL_NUM(total_pixel) | v_CABC_TOTAL_NUM(stage_down); - lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val); - - mask = m_CABC_EN | m_CABC_CALC_PIXEL_NUM | - m_CABC_STAGE_UP; - val = v_CABC_EN(1) | v_CABC_CALC_PIXEL_NUM(calc_pixel) | - v_CABC_STAGE_UP(stage_up); - lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} -/* - Sin0=*0.000¡¡¡¡¡¡¡¡ Cos0=*1.000 - Sin5=*0.087¡¡¡¡¡¡¡C Cos5=*0.996 - Sin10=*0.174 Cos10=*0.985 - Sin15=*0.259 ¡¡¡¡¡¡¡CCos15=*0.966 - Sin20=*0.342¡¡¡¡¡¡¡¡Cos20=*0.940 - Sin25=*0.422¡¡¡¡¡¡¡¡Cos25=*0.906 - Sin30=*0.500¡¡¡¡¡¡¡¡Cos30=*0.866 -*/ -static int rk3288_lcdc_set_hue(struct rk_lcdc_driver *dev_drv,int hue) -{ - - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - int sin_hue_val,cos_hue_val; - u32 mask, val; - //double sin_hue[7]={0.000,0.087,0.174,0.259,0.342,0.422,0.500}; - //double cos_hue[7]={1.000,0.996,0.985,0.966,0.940,0.906,0.866}; - int sin_hue[7]={0,22, 44, 66, 87, 108, 128}; - int cos_hue[7]={256,254,252,247,240,231,221}; - - if((hue > 0)&&(hue <= 30)){ - //sin_hue_val = (int)sin_hue[hue] * 256; - //cos_hue_val = (int)cos_hue[hue] * 256; - sin_hue_val = sin_hue[hue]; - cos_hue_val = cos_hue[hue]; - }else if((hue > 6)&&(hue <= 13)){ - hue -= 6; - //sin_hue_val = (int)sin_hue[hue] * 256 + 0x100; - //cos_hue_val = (int)cos_hue[hue] * 256 + 0x100; - sin_hue_val = sin_hue[hue] + 0x100; - cos_hue_val = cos_hue[hue] + 0x100; - }else{ - printk("hue=%d should be [0:60]\n",hue); - } - - spin_lock(&lcdc_dev->reg_lock); - - if(lcdc_dev->clk_on){ - - mask = m_BCSH_OUT_MODE; - val = v_BCSH_OUT_MODE(3); - - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - - - mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; - val = v_BCSH_SIN_HUE(sin_hue_val) | v_BCSH_COS_HUE(cos_hue_val); - lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); - - mask = m_BCSH_EN; - val = v_BCSH_EN(1); - lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); - lcdc_cfg_done(lcdc_dev); - } - - spin_unlock(&lcdc_dev->reg_lock); - - return 0; -} - -static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,int bri,int con,int sat) -{ - struct lcdc_device *lcdc_dev = - container_of(dev_drv, struct lcdc_device, driver); - u32 mask, val; - - spin_lock(&lcdc_dev->reg_lock); - if(lcdc_dev->clk_on){ - mask = m_BCSH_OUT_MODE | m_BCSH_BRIGHTNESS | - m_BCSH_CONTRAST | m_BCSH_SAT_CON; - val = v_BCSH_OUT_MODE(3) | v_BCSH_BRIGHTNESS(bri) | - v_BCSH_CONTRAST(con) | v_BCSH_SAT_CON(sat); - lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); - - mask = m_BCSH_EN; - val = v_BCSH_EN(1); - lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); - lcdc_cfg_done(lcdc_dev); - } - spin_unlock(&lcdc_dev->reg_lock); - return 0; -} - - -static struct rk_lcdc_win lcdc_win[] = { - [0] = { - .name = "win0", - .id = 0, - .support_3d = false, - }, - [1] = { - .name = "win1", - .id = 1, - .support_3d = false, - }, - [2] = { - .name = "win2", - .id = 2, - .support_3d = false, - }, - [3] = { - .name = "win3", - .id = 3, - .support_3d = false, - }, -}; - -static struct rk_lcdc_drv_ops lcdc_drv_ops = { - .open = rk3288_lcdc_open, - .load_screen = rk3288_load_screen, - .set_par = rk3288_lcdc_set_par, - .pan_display = rk3288_lcdc_pan_display, - .lcdc_reg_update = rk3288_lcdc_reg_update, - .blank = rk3288_lcdc_blank, - .ioctl = rk3288_lcdc_ioctl, - .suspend = rk3288_lcdc_early_suspend, - .resume = rk3288_lcdc_early_resume, - .get_win_state = rk3288_lcdc_get_win_state, - .ovl_mgr = rk3288_lcdc_ovl_mgr, - .get_disp_info = rk3288_lcdc_get_disp_info, - .fps_mgr = rk3288_lcdc_fps_mgr, - .fb_get_win_id = rk3288_lcdc_get_win_id, - .fb_win_remap = rk3288_fb_win_remap, - .set_dsp_lut = rk3288_set_dsp_lut, - .poll_vblank = rk3288_lcdc_poll_vblank, - .dpi_open = rk3288_lcdc_dpi_open, - .dpi_win_sel = rk3288_lcdc_dpi_win_sel, - .dpi_status = rk3288_lcdc_dpi_status, - .get_dsp_addr = rk3288_lcdc_get_dsp_addr, - .set_dsp_cabc = rk3288_lcdc_set_dsp_cabc, - .set_dsp_hue = rk3288_lcdc_set_hue, - .set_dsp_bcsh_bcs = rk3288_lcdc_set_bcsh_bcs, -}; -static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val) -{ - if (reg_val & m_WIN0_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR, - v_WIN0_EMPTY_INTR_CLR(1)); - printk("win0 empty irq!"); - }else if (reg_val & m_WIN1_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR, - v_WIN1_EMPTY_INTR_CLR(1)); - printk("win1 empty irq!"); - }else if (reg_val & m_WIN2_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR, - v_WIN2_EMPTY_INTR_CLR(1)); - printk("win2 empty irq!"); - }else if (reg_val & m_WIN3_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR, - v_WIN3_EMPTY_INTR_CLR(1)); - printk("win3 empty irq!"); - }else if (reg_val & m_HWC_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR, - v_HWC_EMPTY_INTR_CLR(1)); - printk("HWC empty irq!"); - }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR, - v_POST_BUF_EMPTY_INTR_CLR(1)); - printk("post buf empty irq!"); - }else if (reg_val & m_PWM_GEN_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR, - v_PWM_GEN_INTR_CLR(1)); - printk("PWM gen irq!"); - } - - return 0; -} -static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id) -{ - struct lcdc_device *lcdc_dev = - (struct lcdc_device *)dev_id; - ktime_t timestamp = ktime_get(); - u32 intr0_reg; - intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); - - if (intr0_reg & m_FS_INTR_STS) { - timestamp = ktime_get(); - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR, - v_FS_INTR_CLR(1)); - if (lcdc_dev->driver.wait_fs) { - spin_lock(&(lcdc_dev->driver.cpl_lock)); - complete(&(lcdc_dev->driver.frame_done)); - spin_unlock(&(lcdc_dev->driver.cpl_lock)); - } - lcdc_dev->driver.vsync_info.timestamp = timestamp; - wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); - - } else if (intr0_reg & m_LINE_FLAG_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, - v_LINE_FLAG_INTR_CLR(1)); - } else if (intr0_reg & m_BUS_ERROR_INTR_STS) { - lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR, - v_BUS_ERROR_INTR_CLR(1)); - printk("buf_error_int!"); - } - - /*for debug*/ - #if 0 - intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1); - if(intr1_reg != 0){ - rk3288_lcdc_parse_irq(intr1_reg); - } - #endif - return IRQ_HANDLED; -} - -#if defined(CONFIG_PM) -static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state) -{ - return 0; -} - -static int rk3288_lcdc_resume(struct platform_device *pdev) -{ - return 0; -} -#else -#define rk3288_lcdc_suspend NULL -#define rk3288_lcdc_resume NULL -#endif - -static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev) -{ - struct device_node *np = lcdc_dev->dev->of_node; - int val; - if (of_property_read_u32(np, "rockchip,prop", &val)) - lcdc_dev->prop = PRMRY; /*default set it as primary */ - else - lcdc_dev->prop = val; - - if (of_property_read_u32(np, "rockchip,pwr18", &val)) - lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */ - else - lcdc_dev->pwr18 = (val ? true : false); - return 0; -} - -static int rk3288_lcdc_probe(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = NULL; - struct rk_lcdc_driver *dev_drv; - struct device *dev = &pdev->dev; - struct resource *res; - struct device_node *np = pdev->dev.of_node; - int prop; - int ret = 0; - - /*if the primary lcdc has not registered ,the extend - lcdc register later */ - of_property_read_u32(np, "rockchip,prop", &prop); - if (prop == EXTEND) { - if (!is_prmry_rk_lcdc_registered()) - return -EPROBE_DEFER; - } - lcdc_dev = devm_kzalloc(dev, - sizeof(struct lcdc_device), GFP_KERNEL); - if (!lcdc_dev) { - dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!"); - return -ENOMEM; - } - platform_set_drvdata(pdev, lcdc_dev); - lcdc_dev->dev = dev; - rk3288_lcdc_parse_dt(lcdc_dev); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcdc_dev->reg_phy_base = res->start; - lcdc_dev->len = resource_size(res); - lcdc_dev->regs = devm_ioremap_resource(dev, res); - if (IS_ERR(lcdc_dev->regs)) - return PTR_ERR(lcdc_dev->regs); - - lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); - if (IS_ERR(lcdc_dev->regsbak)) - return PTR_ERR(lcdc_dev->regsbak); - lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR); - lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base); - if (lcdc_dev->id < 0) { - dev_err(&pdev->dev, "no such lcdc device!\n"); - return -ENXIO; - } - dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); - dev_drv = &lcdc_dev->driver; - dev_drv->dev = dev; - dev_drv->prop = prop; - dev_drv->id = lcdc_dev->id; - dev_drv->ops = &lcdc_drv_ops; - dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); - spin_lock_init(&lcdc_dev->reg_lock); - - lcdc_dev->irq = platform_get_irq(pdev, 0); - if (lcdc_dev->irq < 0) { - dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", - lcdc_dev->id); - return -ENXIO; - } - - ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr, - IRQF_DISABLED, dev_name(dev), lcdc_dev); - if (ret) { - dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", - lcdc_dev->irq, ret); - return ret; - } - - ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); - if (ret < 0) { - dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); - return ret; - } - lcdc_dev->screen = dev_drv->screen0; - - dev_info(dev, "lcdc%d probe ok\n", lcdc_dev->id); - - return 0; -} - -static int rk3288_lcdc_remove(struct platform_device *pdev) -{ - - return 0; -} - -static void rk3288_lcdc_shutdown(struct platform_device *pdev) -{ - struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); - - rk3288_lcdc_deint(lcdc_dev); - rk_disp_pwr_disable(&lcdc_dev->driver); -} - -#if defined(CONFIG_OF) -static const struct of_device_id rk3288_lcdc_dt_ids[] = { - {.compatible = "rockchip,rk3288-lcdc",}, - {} -}; -#endif - -static struct platform_driver rk3288_lcdc_driver = { - .probe = rk3288_lcdc_probe, - .remove = rk3288_lcdc_remove, - .driver = { - .name = "rk3288-lcdc", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids), - }, - .suspend = rk3288_lcdc_suspend, - .resume = rk3288_lcdc_resume, - .shutdown = rk3288_lcdc_shutdown, -}; - -static int __init rk3288_lcdc_module_init(void) -{ - return platform_driver_register(&rk3288_lcdc_driver); -} - -static void __exit rk3288_lcdc_module_exit(void) -{ - platform_driver_unregister(&rk3288_lcdc_driver); -} - -fs_initcall(rk3288_lcdc_module_init); -module_exit(rk3288_lcdc_module_exit); - - +/* + * drivers/video/rockchip/lcdc/rk3288_lcdc.c + * + * Copyright (C) 2014 ROCKCHIP, Inc. + *Author:hjc + *This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include "../../../arch/arm/mach-rockchip/cpu.h" +//#include "../../../arch/arm/mach-rockchip/iomap.h" +//#include "../../../arch/arm/mach-rockchip/grf.h" + +#include "rk3288_lcdc.h" + +#if defined(CONFIG_HAS_EARLYSUSPEND) +#include +#endif + +static int dbg_thresd; +module_param(dbg_thresd, int, S_IRUGO | S_IWUSR); + +#define DBG(level, x...) do { \ + if (unlikely(dbg_thresd >= level)) \ + printk(KERN_INFO x); } while (0) + +/*#define WAIT_FOR_SYNC 1*/ + +static int rk3288_lcdc_get_id(u32 phy_base) +{ + if (cpu_is_rk3288()) { + if (phy_base == 0xff940000)/*vop lite*/ +#ifdef CONFIG_RK_FPGA + return 1; +#else + return 0; +#endif + else if (phy_base == 0xff930000)/*vop big*/ +#ifdef CONFIG_RK_FPGA + return 0; +#else + return 1; +#endif + else + return -EINVAL; + } else { + pr_err("un supported platform \n"); + return -EINVAL; + } + +} + +static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv) +{ + int i = 0; + int __iomem *c; + int v; + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct + lcdc_device, + driver); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); + lcdc_cfg_done(lcdc_dev); + mdelay(25); + for (i = 0; i < 256; i++) { + v = dev_drv->cur_screen->dsp_lut[i]; + c = lcdc_dev->dsp_lut_addr_base + i; + writel_relaxed(v, c); + + } + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); + + return 0; + +} + +static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev) +{ +#ifdef CONFIG_RK_FPGA + lcdc_dev->clk_on = 1; + return 0; +#endif + if (!lcdc_dev->clk_on) { + clk_prepare_enable(lcdc_dev->hclk); + clk_prepare_enable(lcdc_dev->dclk); + clk_prepare_enable(lcdc_dev->aclk); + /*clk_enable(lcdc_dev->pd);*/ + spin_lock(&lcdc_dev->reg_lock); + lcdc_dev->clk_on = 1; + spin_unlock(&lcdc_dev->reg_lock); + } + + return 0; +} + +static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev) +{ +#ifdef CONFIG_RK_FPGA + lcdc_dev->clk_on = 0; + return 0; +#endif + if (lcdc_dev->clk_on) { + spin_lock(&lcdc_dev->reg_lock); + lcdc_dev->clk_on = 0; + spin_unlock(&lcdc_dev->reg_lock); + mdelay(25); + clk_disable_unprepare(lcdc_dev->dclk); + clk_disable_unprepare(lcdc_dev->hclk); + clk_disable_unprepare(lcdc_dev->aclk); + /*clk_disable(lcdc_dev->pd);*/ + } + + return 0; +} + +static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev) +{ + u32 mask, val; + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN | + m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN; + val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) | + v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0); + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); + + mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR | + m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR; + val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) | + v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0); + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); + + mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | + m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN | + m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | + m_POST_BUF_EMPTY_INTR_EN; + val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) | + v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) | + v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) | + v_PWM_GEN_INTR_EN(0); + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); + + mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR | + m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR | + m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR | + m_POST_BUF_EMPTY_INTR_CLR; + val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) | + v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) | + v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) | + v_PWM_GEN_INTR_CLR(0); + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); + lcdc_cfg_done(lcdc_dev); + spin_unlock(&lcdc_dev->reg_lock); + } else { + spin_unlock(&lcdc_dev->reg_lock); + } + mdelay(1); + return 0; +} +static void rk3288_lcdc_reg_dump(struct lcdc_device *lcdc_dev) +{ + int *cbase = (int *)lcdc_dev->regs; + int *regsbak = (int *)lcdc_dev->regsbak; + int i, j; + + printk("back up reg:\n"); + for (i = 0; i <= (0x200 >> 4); i++) { + printk("0x%04x: ",i*16); + for (j = 0; j < 4; j++) + printk("%08x ", *(regsbak + i * 4 + j)); + printk("\n"); + } + + printk("lcdc reg:\n"); + for (i = 0; i <= (0x200 >> 4); i++) { + printk("0x%04x: ",i*16); + for (j = 0; j < 4; j++) + printk("%08x ", readl_relaxed(cbase + i * 4 + j)); + printk("\n"); + } + +} + +/********do basic init*********/ +static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv) +{ + int v,i,j; + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct + lcdc_device, + driver); + int *cbase = (int *)lcdc_dev->regs; + if (lcdc_dev->pre_init) + return 0; + + if (lcdc_dev->id == 0) { + /*lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");*/ + lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc0"); + lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc0"); + lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc0"); + } else if (lcdc_dev->id == 1) { + /*lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");*/ + lcdc_dev->hclk = clk_get(NULL, "g_h_lcdc1"); + lcdc_dev->aclk = clk_get(NULL, "aclk_lcdc1"); + lcdc_dev->dclk = clk_get(NULL, "dclk_lcdc1"); + } else { + dev_err(lcdc_dev->dev, "invalid lcdc device!\n"); + return -EINVAL; + } + if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) || + (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { + dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n", + lcdc_dev->id); + } + + /*uboot display has enabled lcdc in boot */ + if (!support_uboot_display()) { + rk_disp_pwr_enable(dev_drv); + rk3288_lcdc_clk_enable(lcdc_dev); + } else { + lcdc_dev->clk_on = 1; + } + + /*rk3288_lcdc_read_reg_defalut_cfg(lcdc_dev);*/ + /*rk3288_lcdc_reg_dump(lcdc_dev);*/ + for (i = 0; i <= (0x200 >> 4); i++) { + for (j = 0; j < 4; j++) + readl_relaxed(cbase + i * 4 + j); + + } +#ifndef CONFIG_RK_FPGA + if (lcdc_dev->pwr18 == true) { + v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/ + writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); + } else { + v = 0x00010000; + writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL); + } +#endif + lcdc_set_bit(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN); + lcdc_cfg_done(lcdc_dev); + lcdc_dev->pre_init = true; + + return 0; +} + +static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev) +{ + + + rk3288_lcdc_disable_irq(lcdc_dev); + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + lcdc_dev->clk_on = 0; + lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN); + lcdc_cfg_done(lcdc_dev); + spin_unlock(&lcdc_dev->reg_lock); + } else { + spin_unlock(&lcdc_dev->reg_lock); + } + mdelay(1); +} +static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_screen *screen = dev_drv->cur_screen; + u16 x_res = screen->mode.xres; + u16 y_res = screen->mode.yres; + u32 mask, val; + u16 h_total,v_total; + u16 post_hsd_en,post_vsd_en; + u16 post_dsp_hact_st,post_dsp_hact_end; + u16 post_dsp_vact_st,post_dsp_vact_end; + u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1; + u16 post_h_fac,post_v_fac; + + h_total = screen->mode.hsync_len+screen->mode.left_margin + + x_res + screen->mode.right_margin; + v_total = screen->mode.vsync_len+screen->mode.upper_margin + + y_res + screen->mode.lower_margin; + + if(screen->post_dsp_stx + screen->post_xsize > x_res){ + dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n", + screen->post_dsp_stx,screen->post_xsize,x_res); + screen->post_dsp_stx = x_res - screen->post_xsize; + } + if(screen->x_mirror == 0){ + post_dsp_hact_st=screen->post_dsp_stx + + screen->mode.hsync_len+screen->mode.left_margin; + post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize; + }else{ + post_dsp_hact_st = h_total - screen->post_dsp_stx - + screen->mode.hsync_len-screen->mode.left_margin; + post_dsp_hact_end = post_dsp_hact_st - screen->post_xsize; + } + if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){ + post_hsd_en = 1; + post_h_fac = + GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize); + }else{ + post_hsd_en = 0; + post_h_fac = 0x1000; + } + + + if(screen->post_dsp_sty + screen->post_ysize > y_res){ + dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n", + screen->post_dsp_sty,screen->post_ysize,y_res); + screen->post_dsp_sty = y_res - screen->post_ysize; + } + + if(screen->y_mirror == 0){ + post_dsp_vact_st = screen->post_dsp_sty + + screen->mode.vsync_len+screen->mode.upper_margin; + post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize; + }else{ + post_dsp_vact_st = v_total - screen->post_dsp_sty - + screen->mode.vsync_len-screen->mode.upper_margin; + post_dsp_vact_end = post_dsp_vact_st - screen->post_ysize; + } + if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){ + post_vsd_en = 1; + post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize); + }else{ + post_vsd_en = 0; + post_v_fac = 0x1000; + } + + if(screen->interlace == 1){ + post_dsp_vact_st_f1 = v_total + post_dsp_vact_st; + post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize; + }else{ + post_dsp_vact_st_f1 = 0; + post_dsp_vact_end_f1 = 0; + } + DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d," + "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n", + screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos, + post_hsd_en,post_h_fac,post_vsd_en,post_v_fac); + mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST; + val = v_DSP_HACT_END_POST(post_dsp_hact_end) | + v_DSP_HACT_ST_POST(post_dsp_hact_st); + lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val); + + mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST; + val = v_DSP_VACT_END_POST(post_dsp_vact_end) | + v_DSP_VACT_ST_POST(post_dsp_vact_st); + lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val); + + mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB; + val = v_POST_HS_FACTOR_YRGB(post_h_fac) | + v_POST_VS_FACTOR_YRGB(post_v_fac); + lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val); + + mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1; + val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) | + v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1); + lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val); + + mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN; + val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en); + lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val); + return 0; +} + +static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct + lcdc_device, + driver); + struct rk_lcdc_win *win; + u32 colorkey_r,colorkey_g,colorkey_b; + int i,key_val; + for(i=0;i<4;i++){ + win = dev_drv->win[i]; + key_val = win->color_key_val; + colorkey_r = (key_val & 0xff)<<2; + colorkey_g = ((key_val>>8)&0xff)<<12; + colorkey_b = ((key_val>>16)&0xff)<<22; + /*color key dither 565/888->aaa*/ + key_val = colorkey_r | colorkey_g | colorkey_b; + switch(i){ + case 0: + lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val); + break; + case 1: + lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val); + break; + case 2: + lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val); + break; + case 3: + lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val); + break; + default: + break; + } + } + return 0; +} + +static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_lcdc_win *win = dev_drv->win[win_id]; + struct alpha_config alpha_config; + + u32 mask, val; + int ppixel_alpha,global_alpha; + u32 src_alpha_ctl,dst_alpha_ctl; + ppixel_alpha = ((win->format == ARGB888)||(win->format == ABGR888)) ? 1 : 0; + global_alpha = (win->g_alpha_val == 0) ? 0 : 1; + alpha_config.src_global_alpha_val = win->g_alpha_val; + switch(win->alpha_mode){ + case AB_USER_DEFINE: + break; + case AB_CLEAR: + alpha_config.src_factor_mode=AA_ZERO; + alpha_config.dst_factor_mode=AA_ZERO; + break; + case AB_SRC: + alpha_config.src_factor_mode=AA_ONE; + alpha_config.dst_factor_mode=AA_ZERO; + break; + case AB_DST: + alpha_config.src_factor_mode=AA_ZERO; + alpha_config.dst_factor_mode=AA_ONE; + break; + case AB_SRC_OVER: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_ONE; + alpha_config.dst_factor_mode=AA_SRC_INVERSE; + break; + case AB_DST_OVER: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC_INVERSE; + alpha_config.dst_factor_mode=AA_ONE; + break; + case AB_SRC_IN: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC; + alpha_config.dst_factor_mode=AA_ZERO; + break; + case AB_DST_IN: + alpha_config.src_factor_mode=AA_ZERO; + alpha_config.dst_factor_mode=AA_SRC; + break; + case AB_SRC_OUT: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC_INVERSE; + alpha_config.dst_factor_mode=AA_ZERO; + break; + case AB_DST_OUT: + alpha_config.src_factor_mode=AA_ZERO; + alpha_config.dst_factor_mode=AA_SRC_INVERSE; + break; + case AB_SRC_ATOP: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC; + alpha_config.dst_factor_mode=AA_SRC_INVERSE; + break; + case AB_DST_ATOP: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC_INVERSE; + alpha_config.dst_factor_mode=AA_SRC; + break; + case XOR: + alpha_config.src_color_mode=AA_SRC_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC_INVERSE; + alpha_config.dst_factor_mode=AA_SRC_INVERSE; + break; + case AB_SRC_OVER_GLOBAL: + alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL; + alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL; + alpha_config.src_factor_mode=AA_SRC_GLOBAL; + alpha_config.dst_factor_mode=AA_SRC_INVERSE; + break; + default: + pr_err("alpha mode error\n"); + break; + } + if((ppixel_alpha == 1)&&(global_alpha == 1)){ + alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL; + }else if(ppixel_alpha == 1){ + alpha_config.src_global_alpha_mode = AA_PER_PIX; + }else if(global_alpha == 1){ + alpha_config.src_global_alpha_mode = AA_GLOBAL; + }else{ + dev_warn(lcdc_dev->dev,"alpha_en should be 0\n"); + } + alpha_config.src_alpha_mode = AA_STRAIGHT; + alpha_config.src_alpha_sel = AA_NO_SAT; + + switch(win_id){ + case 0: + src_alpha_ctl = 0x60; + dst_alpha_ctl = 0x64; + break; + case 1: + src_alpha_ctl = 0xa0; + dst_alpha_ctl = 0xa4; + break; + case 2: + src_alpha_ctl = 0xdc; + dst_alpha_ctl = 0xec; + break; + case 3: + src_alpha_ctl = 0x12c; + dst_alpha_ctl = 0x13c; + break; + } + mask = m_WIN0_DST_FACTOR_M0; + val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode); + lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val); + mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 | + m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 | + m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0| + m_WIN0_SRC_GLOBAL_ALPHA; + val = v_WIN0_SRC_ALPHA_EN(1) | + v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) | + v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) | + v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) | + v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) | + v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val); + lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val); + + return 0; +} + +static int rk3288_win_full_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_lcdc_win *win = dev_drv->win[win_id]; + unsigned int mask, val, off; + off = win_id * 0x40; + + if(win->state == 1){ + mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 | + m_WIN0_LB_MODE | m_WIN0_RB_SWAP; + val = v_WIN0_EN(win->state) | v_WIN0_DATA_FMT(win->fmt_cfg) | + v_WIN0_FMT_10(win->fmt_10) | + v_WIN0_LB_MODE(win->win_lb_mode) | + v_WIN0_RB_SWAP(win->swap_rb); + lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); + + mask = m_WIN0_BIC_COE_SEL | + m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 | + m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT4 | + m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE | + m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE | + m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE | + m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE | + m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE; + val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) | + v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) | + v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) | + v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) | + v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) | + v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) | + v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) | + v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) | + v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) | + v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) | + v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) | + v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) | + v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) | + v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) | + v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode); + lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val); + + val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) | + v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride); + lcdc_writel(lcdc_dev, WIN0_VIR+off, val); + lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr); + lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr); + val = v_WIN0_ACT_WIDTH(win->area[0].xact) | + v_WIN0_ACT_HEIGHT(win->area[0].yact); + lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val); + + val = v_WIN0_DSP_WIDTH(win->area[0].xsize) | + v_WIN0_DSP_HEIGHT(win->area[0].ysize); + lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val); + + val = v_WIN0_DSP_XST(win->area[0].dsp_stx) | + v_WIN0_DSP_YST(win->area[0].dsp_sty); + lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val); + + val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) | + v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y); + lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val); + + val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) | + v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y); + lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val); + if(win->alpha_en == 1) + rk3288_lcdc_alpha_cfg(dev_drv,win_id); + else{ + mask = m_WIN0_SRC_ALPHA_EN; + val = v_WIN0_SRC_ALPHA_EN(0); + lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val); + } + /*offset*/ + }else{ + mask = m_WIN0_EN; + val = v_WIN0_EN(win->state); + lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val); + } + return 0; +} + +static int rk3288_win_lite_reg_update(struct rk_lcdc_driver *dev_drv,int win_id) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_lcdc_win *win = dev_drv->win[win_id]; + unsigned int mask, val, off; + off = (win_id-2) * 0x50; + + if(win->state == 1){ + mask = m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP; + val = v_WIN2_EN(1) | v_WIN2_DATA_FMT(win->fmt_cfg) | + v_WIN2_RB_SWAP(win->swap_rb); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + /*area 0*/ + if(win->area[0].state == 1){ + mask = m_WIN2_MST0_EN; + val = v_WIN2_MST0_EN(1); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + + mask = m_WIN2_VIR_STRIDE0; + val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride); + lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); + + lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr); + val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) | + v_WIN2_DSP_HEIGHT0(win->area[0].ysize); + lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val); + val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) | + v_WIN2_DSP_YST0(win->area[0].dsp_sty); + lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val); + }else{ + mask = m_WIN2_MST0_EN; + val = v_WIN2_MST0_EN(0); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + } + /*area 1*/ + if(win->area[1].state == 1){ + mask = m_WIN2_MST1_EN; + val = v_WIN2_MST1_EN(1); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + + mask = m_WIN2_VIR_STRIDE1; + val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride); + lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val); + + lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr); + val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) | + v_WIN2_DSP_HEIGHT1(win->area[1].ysize); + lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val); + val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) | + v_WIN2_DSP_YST1(win->area[1].dsp_sty); + lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val); + }else{ + mask = m_WIN2_MST1_EN; + val = v_WIN2_MST1_EN(0); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + } + /*area 2*/ + if(win->area[2].state == 1){ + mask = m_WIN2_MST2_EN; + val = v_WIN2_MST2_EN(1); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + + mask = m_WIN2_VIR_STRIDE2; + val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride); + lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); + + lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr); + val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) | + v_WIN2_DSP_HEIGHT2(win->area[2].ysize); + lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val); + val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) | + v_WIN2_DSP_YST2(win->area[2].dsp_sty); + lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val); + }else{ + mask = m_WIN2_MST2_EN; + val = v_WIN2_MST2_EN(0); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + } + /*area 3*/ + if(win->area[3].state == 1){ + mask = m_WIN2_MST3_EN; + val = v_WIN2_MST3_EN(1); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + + mask = m_WIN2_VIR_STRIDE3; + val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride); + lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val); + + lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr); + val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) | + v_WIN2_DSP_HEIGHT3(win->area[3].ysize); + lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val); + val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) | + v_WIN2_DSP_YST3(win->area[3].dsp_sty); + lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val); + }else{ + mask = m_WIN2_MST3_EN; + val = v_WIN2_MST3_EN(0); + lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val); + } + + if(win->alpha_en == 1) + rk3288_lcdc_alpha_cfg(dev_drv,win_id); + else{ + mask = m_WIN2_SRC_ALPHA_EN; + val = v_WIN2_SRC_ALPHA_EN(0); + lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val); + } + }else{ + mask = m_WIN2_EN | m_WIN2_MST0_EN | + m_WIN2_MST0_EN | m_WIN2_MST2_EN | + m_WIN2_MST3_EN; + val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) | + v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | + v_WIN2_MST3_EN(0); + lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val); + } + return 0; +} + +static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + int timeout; + unsigned long flags; + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)) + { + lcdc_dev->standby = 0; + lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, + v_STANDBY_EN(lcdc_dev->standby)); + rk3288_win_full_reg_update(dev_drv,0); + rk3288_win_full_reg_update(dev_drv,1); + rk3288_win_lite_reg_update(dev_drv,2); + rk3288_win_lite_reg_update(dev_drv,3); + rk3288_lcdc_post_cfg(dev_drv); + lcdc_cfg_done(lcdc_dev); + } + spin_unlock(&lcdc_dev->reg_lock); + + if (dev_drv->wait_fs) { + spin_lock_irqsave(&dev_drv->cpl_lock, flags); + init_completion(&dev_drv->frame_done); + spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); + timeout = wait_for_completion_timeout(&dev_drv->frame_done, + msecs_to_jiffies + (dev_drv->cur_screen->ft + + 5)); + if (!timeout && (!dev_drv->frame_done.done)) { + dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n"); + return -ETIMEDOUT; + } + } + DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id); + return 0; + +} + +static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev) +{ + memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x84); + return 0; +} + +static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen) +{ + int ret = -EINVAL; + int fps; + u16 face = 0; + u32 v=0; + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_screen *screen = dev_drv->cur_screen; + u16 hsync_len = screen->mode.hsync_len; + u16 left_margin = screen->mode.left_margin; + u16 right_margin = screen->mode.right_margin; + u16 vsync_len = screen->mode.vsync_len; + u16 upper_margin = screen->mode.upper_margin; + u16 lower_margin = screen->mode.lower_margin; + u16 x_res = screen->mode.xres; + u16 y_res = screen->mode.yres; + u32 mask, val; + u16 h_total,v_total; + + h_total = hsync_len + left_margin + x_res + right_margin; + v_total = vsync_len + upper_margin + y_res + lower_margin; + screen->post_dsp_stx=0; + screen->post_dsp_sty=0; + screen->post_xsize =x_res; + screen->post_ysize = y_res; + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + switch (screen->face) { + case OUT_P565: + face = OUT_P565; + mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | + m_DITHER_DOWN_SEL; + val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | + v_DITHER_DOWN_SEL(1); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + break; + case OUT_P666: + face = OUT_P666; + mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | + m_DITHER_DOWN_SEL; + val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | + v_DITHER_DOWN_SEL(1); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + break; + case OUT_D888_P565: + face = OUT_P888; + mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | + m_DITHER_DOWN_SEL; + val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) | + v_DITHER_DOWN_SEL(1); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + break; + case OUT_D888_P666: + face = OUT_P888; + mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE | + m_DITHER_DOWN_SEL; + val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) | + v_DITHER_DOWN_SEL(1); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + break; + case OUT_P888: + face = OUT_P888; + mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN; + val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + break; + default: + dev_err(lcdc_dev->dev,"un supported interface!\n"); + break; + } + switch(screen->type){ + case SCREEN_RGB: + case SCREEN_LVDS: + case SCREEN_DUAL_LVDS: + mask = m_RGB_OUT_EN; + val = v_RGB_OUT_EN(1); + /*v = 1 << (3+16); + v |= (lcdc_dev->id << 3);*/ + break; + case SCREEN_HDMI: + mask = m_HDMI_OUT_EN; + val = v_HDMI_OUT_EN(1); + /*v = 1 << (4+16); + v |= (lcdc_dev->id << 4);*/ + break; + case SCREEN_MIPI: + mask = m_MIPI_OUT_EN; + val = v_MIPI_OUT_EN(1); + /*v = (1 << (6+16))||(1 << (9+16)); + v |= (lcdc_dev->id << 6); + v |= (lcdc_dev->id << 9);*/ + break; + case SCREEN_DUAL_MIPI: + mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN; + val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1); + /*v = (1 << (6+16))||(1 << (9+16)); + v |= (lcdc_dev->id << 6); + v |= (lcdc_dev->id << 9);*/ + break; + case SCREEN_EDP: + face = OUT_RGB_AAA; /*RGB AAA output*/ + mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN; + val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val); + mask = m_EDP_OUT_EN; + val = v_EDP_OUT_EN(1); + /*v = 1 << (5+16); + v |= (lcdc_dev->id << 5);*/ + break; + } + lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val); +#ifndef CONFIG_RK_FPGA + writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); +#endif + mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL | + m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP | + m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | + m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN | + m_DSP_BLACK_EN; + val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) | + v_DSP_VSYNC_POL(screen->pin_vsync) | + v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) | + v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) | + v_DSP_RG_SWAP(screen->swap_rg) | + v_DSP_DELTA_SWAP(screen->swap_delta) | + v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) | + v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0);; + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val); + + mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED; + val = v_DSP_BG_BLUE(0x3ff) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0); + lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val); + + mask = m_DSP_HS_PW | m_DSP_HTOTAL; + val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total); + lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val); + + mask = m_DSP_HACT_END | m_DSP_HACT_ST; + val = v_DSP_HACT_END(hsync_len + left_margin + x_res) | + v_DSP_HACT_ST(hsync_len + left_margin); + lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val); + + mask = m_DSP_VS_PW | m_DSP_VTOTAL; + val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total); + lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val); + + mask = m_DSP_VACT_END | m_DSP_VACT_ST; + val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) | + v_DSP_VACT_ST(vsync_len + upper_margin); + lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val); + + rk3288_lcdc_post_cfg(dev_drv); + } + spin_unlock(&lcdc_dev->reg_lock); + +#ifndef CONFIG_RK_FPGA + ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock); + if (ret) + dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id); + lcdc_dev->pixclock = + div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + lcdc_dev->driver.pixclock = lcdc_dev->pixclock; + + fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock); + screen->ft = 1000 / fps; + dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ", + lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps); + + if (screen->init) + screen->init(); +#endif + return 0; +} + +/*enable layer,open:1,enable;0 disable*/ +static int win0_open(struct lcdc_device *lcdc_dev, bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + if (open) { + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "wakeup from standby!\n"); + lcdc_dev->standby = 0; + } + lcdc_dev->atv_layer_cnt++; + } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.win[0]->state = open; + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); + lcdc_dev->standby = 1; + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win1_open(struct lcdc_device *lcdc_dev, bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + if (open) { + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "wakeup from standby!\n"); + lcdc_dev->standby = 0; + } + lcdc_dev->atv_layer_cnt++; + } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.win[1]->state = open; + + /*if no layer used,disable lcdc*/ + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); + lcdc_dev->standby = 1; + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win2_open(struct lcdc_device *lcdc_dev, bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + if (open) { + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "wakeup from standby!\n"); + lcdc_dev->standby = 0; + } + lcdc_dev->atv_layer_cnt++; + } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.win[2]->state = open; + + /*if no layer used,disable lcdc*/ + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); + lcdc_dev->standby = 1; + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win3_open(struct lcdc_device *lcdc_dev, bool open) +{ + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + if (open) { + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "wakeup from standby!\n"); + lcdc_dev->standby = 0; + } + lcdc_dev->atv_layer_cnt++; + } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) { + lcdc_dev->atv_layer_cnt--; + } + lcdc_dev->driver.win[3]->state = open; + + /*if no layer used,disable lcdc*/ + if (!lcdc_dev->atv_layer_cnt) { + dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n"); + lcdc_dev->standby = 1; + } + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + + +static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id, + bool open) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct lcdc_device, driver); + + /*enable clk,when first layer open */ + if ((open) && (!lcdc_dev->atv_layer_cnt)) { + rk3288_lcdc_pre_init(dev_drv); + rk3288_lcdc_clk_enable(lcdc_dev); + rk3288_lcdc_reg_restore(lcdc_dev); + rk3288_load_screen(dev_drv, 1); + spin_lock(&lcdc_dev->reg_lock); + if (dev_drv->cur_screen->dsp_lut) + rk3288_lcdc_set_lut(dev_drv); + spin_unlock(&lcdc_dev->reg_lock); + } + + if (win_id == 0) + win0_open(lcdc_dev, open); + else if (win_id == 1) + win1_open(lcdc_dev, open); + else if (win_id == 2) + win2_open(lcdc_dev, open); + else if (win_id == 3) + win3_open(lcdc_dev, open); + else + dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id); + + /*when all layer closed,disable clk */ + if ((!open) && (!lcdc_dev->atv_layer_cnt)) { + rk3288_lcdc_disable_irq(lcdc_dev); + rk3288_lcdc_reg_update(dev_drv); + rk3288_lcdc_clk_disable(lcdc_dev); + } + + return 0; +} + +static int win0_display(struct lcdc_device *lcdc_dev, + struct rk_lcdc_win *win) +{ + u32 y_addr; + u32 uv_addr; + y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/ + uv_addr = win->area[0].cbr_start + win->area[0].c_offset; + DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n", + lcdc_dev->id, __func__, y_addr, uv_addr); + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + win->area[0].y_addr = y_addr; + win->area[0].uv_addr = uv_addr; + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; + +} + +static int win1_display(struct lcdc_device *lcdc_dev, + struct rk_lcdc_win *win) +{ + u32 y_addr; + u32 uv_addr; + y_addr = win->area[0].smem_start + win->area[0].y_offset; + uv_addr = win->area[0].cbr_start + win->area[0].c_offset; + DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n", + lcdc_dev->id, __func__, y_addr, uv_addr); + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) + win->area[0].y_addr = y_addr; + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int win2_display(struct lcdc_device *lcdc_dev, + struct rk_lcdc_win *win) +{ + u32 i,y_addr; + y_addr = win->area[0].smem_start + win->area[0].y_offset; + DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", + lcdc_dev->id, __func__, y_addr); + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) + for(i=0;iarea_num;i++){ + win->area[i].y_addr = + win->area[i].smem_start + win->area[i].y_offset; + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int win3_display(struct lcdc_device *lcdc_dev, + struct rk_lcdc_win *win) +{ + u32 i,y_addr; + y_addr = win->area[0].smem_start + win->area[0].y_offset; + DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n", + lcdc_dev->id, __func__, y_addr); + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) + for(i=0;iarea_num;i++){ + win->area[i].y_addr = + win->area[i].smem_start + win->area[i].y_offset; + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + + +static int rk3288_lcdc_win_display(struct rk_lcdc_driver *dev_drv, struct rk_lcdc_win *win,int win_id) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct lcdc_device, driver); + struct rk_screen *screen = dev_drv->cur_screen; + u32 mask, val; + + lcdc_dev->atv_layer_cnt = dev_drv->atv_layer_cnt; + if(!screen){ + dev_err(dev_drv->dev, "screen is null!\n"); + return -ENOENT; + } + /*overlay*/ + if(win_id == 0){ + win0_display(lcdc_dev, win); + }else if(win_id == 1){ + win1_display(lcdc_dev, win); + }else if(win_id == 2){ + win2_display(lcdc_dev, win); + }else if(win_id == 3){ + win3_display(lcdc_dev, win); + }else{ + dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); + return -EINVAL; + } + /*this is the first frame of the system ,enable frame start interrupt */ + if ((dev_drv->first_frame)) { + dev_drv->first_frame = 0; + mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR | + m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR | + m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM; + val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) | + v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) | + v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin + + screen->mode.yres -1); + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); +#ifdef CONFIG_RK_FPGA + mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN | + m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | + m_PWM_GEN_INTR_EN; + val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) | + v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) | + v_PWM_GEN_INTR_EN(1); + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); +#endif + lcdc_cfg_done(lcdc_dev); + + } + return 0; +} + +static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct lcdc_device, driver); + struct rk_lcdc_win *win = NULL; + struct rk_screen *screen = dev_drv->cur_screen; + u32 mask, val; +#if defined(WAIT_FOR_SYNC) + int timeout; + unsigned long flags; +#endif + win = dev_drv->win[win_id]; + lcdc_dev->atv_layer_cnt = dev_drv->atv_layer_cnt; + if (!screen) { + dev_err(dev_drv->dev, "screen is null!\n"); + return -ENOENT; + } + /*overlay*/ + if(win_id == 0){ + win0_display(lcdc_dev, win); + }else if(win_id == 1){ + win1_display(lcdc_dev, win); + }else if(win_id == 2){ + win2_display(lcdc_dev, win); + }else if(win_id == 3){ + win3_display(lcdc_dev, win); + }else{ + dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id); + return -EINVAL; + } + + + + /*this is the first frame of the system ,enable frame start interrupt */ + if ((dev_drv->first_frame)) { + dev_drv->first_frame = 0; + mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR | + m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR | + m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM; + val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) | + v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) | + v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin + + screen->mode.yres -1); + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val); + #ifdef CONFIG_RK_FPGA + mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN | + m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN | + m_PWM_GEN_INTR_EN; + val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) | + v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) | + v_PWM_GEN_INTR_EN(1); + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val); +#endif + lcdc_cfg_done(lcdc_dev); + } +#if defined(WAIT_FOR_SYNC) + spin_lock_irqsave(&dev_drv->cpl_lock, flags); + init_completion(&dev_drv->frame_done); + spin_unlock_irqrestore(&dev_drv->cpl_lock, flags); + timeout = wait_for_completion_timeout(&dev_drv->frame_done, + msecs_to_jiffies(dev_drv-> + cur_screen->ft + + 5)); + if (!timeout && (!dev_drv->frame_done.done)) { + dev_info(dev_drv->dev, "wait for new frame start time out!\n"); + return -ETIMEDOUT; + } +#endif + dev_drv->ops->ovl_mgr(dev_drv, 0, 1); + rk3288_lcdc_reg_update(dev_drv); + return 0; +} + +static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win) +{ + u16 srcW; + u16 srcH; + u16 dstW; + u16 dstH; + u16 yrgb_srcW; + u16 yrgb_srcH; + u16 yrgb_dstW; + u16 yrgb_dstH; + u32 yrgb_vScaleDnMult; + u32 yrgb_xscl_factor; + u32 yrgb_yscl_factor; + u8 yrgb_vsd_bil_gt2=0; + u8 yrgb_vsd_bil_gt4=0; + + u16 cbcr_srcW; + u16 cbcr_srcH; + u16 cbcr_dstW; + u16 cbcr_dstH; + u32 cbcr_vScaleDnMult; + u32 cbcr_xscl_factor; + u32 cbcr_yscl_factor; + u8 cbcr_vsd_bil_gt2=0; + u8 cbcr_vsd_bil_gt4=0; + + + srcW = win->area[0].xact; + srcH = win->area[0].yact; + dstW = win->area[0].xsize; + dstH = win->area[0].ysize; + + /*yrgb scl mode*/ + yrgb_srcW = srcW; + yrgb_srcH = srcH; + yrgb_dstW = dstW; + yrgb_dstH = dstH; + if(yrgb_srcW < yrgb_dstW){ + win->yrgb_hor_scl_mode = SCALE_UP; + }else if(yrgb_srcW > yrgb_dstW){ + win->yrgb_hor_scl_mode = SCALE_DOWN; + }else{ + win->yrgb_hor_scl_mode = SCALE_NONE; + } + + if(yrgb_srcH < yrgb_dstH){ + win->yrgb_ver_scl_mode = SCALE_UP; + }else if (yrgb_srcH > yrgb_dstH){ + win->yrgb_ver_scl_mode = SCALE_DOWN; + }else{ + win->yrgb_ver_scl_mode = SCALE_NONE; + } + + /*cbcr scl mode*/ + switch (win->format) { + case YUV422: + cbcr_srcW = srcW/2; + cbcr_dstW = dstW; + cbcr_srcH = srcH; + cbcr_dstH = dstH; + break; + case YUV420: + cbcr_srcW = srcW/2; + cbcr_dstW = dstW; + cbcr_srcH = srcH/2; + cbcr_dstH = dstH; + break; + case YUV444: + cbcr_srcW = srcW; + cbcr_dstW = dstW; + cbcr_srcH = srcH; + cbcr_dstH = dstH; + break; + default: + cbcr_srcW = 0; + cbcr_dstW = 0; + cbcr_srcH = 0; + cbcr_dstH = 0; + break; + } + if(cbcr_srcW < cbcr_dstW){ + win->cbr_hor_scl_mode = SCALE_UP; + }else if(cbcr_srcW > cbcr_dstW){ + win->cbr_hor_scl_mode = SCALE_DOWN; + }else{ + win->cbr_hor_scl_mode = SCALE_NONE; + } + + if(cbcr_srcH < cbcr_dstH){ + win->cbr_ver_scl_mode = SCALE_UP; + }else if(cbcr_srcH > cbcr_dstH){ + win->cbr_ver_scl_mode = SCALE_DOWN; + }else{ + win->cbr_ver_scl_mode = SCALE_NONE; + } + DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n" + "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" + "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n" + ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW, + yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode, + cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH, + win->cbr_hor_scl_mode,win->cbr_ver_scl_mode); + + /*line buffer mode*/ + if((win->format == YUV422) || (win->format == YUV420)){ + if(win->cbr_hor_scl_mode == SCALE_DOWN){ + if(cbcr_dstW > 3840){ + pr_err("ERROR cbcr_dst_width exceeds 3840\n"); + }else if(cbcr_dstW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(cbcr_dstW > 1920){ + if(win->yrgb_hor_scl_mode == SCALE_DOWN){ + if(yrgb_dstW > 3840){ + pr_err("ERROR yrgb_dst_width exceeds 3840\n"); + }else if(yrgb_dstW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(yrgb_dstW > 1920){ + win->win_lb_mode = LB_RGB_2560X4; + }else{ + pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); + } + } + }else if(cbcr_dstW > 1280){ + win->win_lb_mode = LB_YUV_3840X5; + }else{ + win->win_lb_mode = LB_YUV_2560X8; + } + } else { /*SCALE_UP or SCALE_NONE*/ + if(cbcr_srcW > 3840){ + pr_err("ERROR cbcr_act_width exceeds 3840\n"); + }else if(cbcr_srcW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(cbcr_srcW > 1920){ + if(win->yrgb_hor_scl_mode == SCALE_DOWN){ + if(yrgb_dstW > 3840){ + pr_err("ERROR yrgb_dst_width exceeds 3840\n"); + }else if(yrgb_dstW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(yrgb_dstW > 1920){ + win->win_lb_mode = LB_RGB_2560X4; + }else{ + pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n"); + } + } + }else if(cbcr_srcW > 1280){ + win->win_lb_mode = LB_YUV_3840X5; + }else{ + win->win_lb_mode = LB_YUV_2560X8; + } + } + }else { + if(win->yrgb_hor_scl_mode == SCALE_DOWN){ + if(yrgb_dstW > 3840){ + pr_err("ERROR yrgb_dsp_width exceeds 3840\n"); + }else if(yrgb_dstW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(yrgb_dstW > 1920){ + win->win_lb_mode = LB_RGB_2560X4; + }else if(yrgb_dstW > 1280){ + win->win_lb_mode = LB_RGB_1920X5; + }else{ + win->win_lb_mode = LB_RGB_1280X8; + } + }else{ /*SCALE_UP or SCALE_NONE*/ + if(yrgb_srcW > 3840){ + pr_err("ERROR yrgb_act_width exceeds 3840\n"); + }else if(yrgb_srcW > 2560){ + win->win_lb_mode = LB_RGB_3840X2; + }else if(yrgb_srcW > 1920){ + win->win_lb_mode = LB_RGB_2560X4; + }else if(yrgb_srcW > 1280){ + win->win_lb_mode = LB_RGB_1920X5; + }else{ + win->win_lb_mode = LB_RGB_1280X8; + } + } + } + DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode); + + /*vsd/vsu scale ALGORITHM*/ + win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/ + win->cbr_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/ + win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/ + win->cbr_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/ + switch(win->win_lb_mode){ + case LB_YUV_3840X5: + case LB_YUV_2560X8: + case LB_RGB_1920X5: + case LB_RGB_1280X8: + win->yrgb_vsu_mode = SCALE_UP_BIC; + win->cbr_vsu_mode = SCALE_UP_BIC; + break; + case LB_RGB_3840X2: + if(win->yrgb_ver_scl_mode != SCALE_NONE) { + pr_err("ERROR : not allow yrgb ver scale\n"); + } + if(win->cbr_ver_scl_mode != SCALE_NONE) { + pr_err("ERROR : not allow cbcr ver scale\n"); + } + break; + case LB_RGB_2560X4: + win->yrgb_vsu_mode = SCALE_UP_BIL; + win->cbr_vsu_mode = SCALE_UP_BIL; + break; + default: + break; + } + DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n", + win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode, + win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode); + + /*SCALE FACTOR*/ + + /*(1.1)YRGB HOR SCALE FACTOR*/ + switch(win->yrgb_hor_scl_mode){ + case SCALE_NONE: + yrgb_xscl_factor = (1<yrgb_hsd_mode) + { + case SCALE_DOWN_BIL: + yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW); + break; + case SCALE_DOWN_AVG: + yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW); + break; + default : + break; + } + break; + default : + break; + } /*win->yrgb_hor_scl_mode*/ + + /*(1.2)YRGB VER SCALE FACTOR*/ + switch(win->yrgb_ver_scl_mode) + { + case SCALE_NONE: + yrgb_yscl_factor = (1<yrgb_vsu_mode) + { + case SCALE_UP_BIL: + yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH); + break; + case SCALE_UP_BIC: + if(yrgb_srcH < 3){ + pr_err("yrgb_srcH should be greater than 3 !!!\n"); + } + yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH); + break; + default : + break; + } + break; + case SCALE_DOWN: + switch(win->yrgb_vsd_mode) + { + case SCALE_DOWN_BIL: + yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH); + yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult); + if(yrgb_vScaleDnMult == 4){ + yrgb_vsd_bil_gt4 = 1; + yrgb_vsd_bil_gt2 = 0; + }else if(yrgb_vScaleDnMult == 2){ + yrgb_vsd_bil_gt4 = 0; + yrgb_vsd_bil_gt2 = 1; + }else{ + yrgb_vsd_bil_gt4 = 0; + yrgb_vsd_bil_gt2 = 0; + } + break; + case SCALE_DOWN_AVG: + yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH); + break; + default: + break; + } /*win->yrgb_vsd_mode*/ + break; + default : + break; + } + win->scale_yrgb_x = yrgb_xscl_factor; + win->scale_yrgb_y = yrgb_yscl_factor; + win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4; + win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2; + DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor, + yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2); + + /*(2.1)CBCR HOR SCALE FACTOR*/ + switch(win->cbr_hor_scl_mode) + { + case SCALE_NONE: + cbcr_xscl_factor = (1<cbr_hsd_mode) + { + case SCALE_DOWN_BIL: + cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW); + break; + case SCALE_DOWN_AVG: + cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW); + break; + default : + break; + } + break; + default : + break; + } /*win->cbr_hor_scl_mode*/ + + /*(2.2)CBCR VER SCALE FACTOR*/ + switch(win->cbr_ver_scl_mode) + { + case SCALE_NONE: + cbcr_yscl_factor = (1<cbr_vsu_mode) + { + case SCALE_UP_BIL: + cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH); + break; + case SCALE_UP_BIC: + if(cbcr_srcH < 3) { + pr_err("cbcr_srcH should be greater than 3 !!!\n"); + } + cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH); + break; + default : + break; + } + break; + case SCALE_DOWN: + switch(win->cbr_vsd_mode) + { + case SCALE_DOWN_BIL: + cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH); + cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult); + if(cbcr_vScaleDnMult == 4){ + cbcr_vsd_bil_gt4 = 1; + cbcr_vsd_bil_gt2 = 0; + }else if(cbcr_vScaleDnMult == 2){ + cbcr_vsd_bil_gt4 = 0; + cbcr_vsd_bil_gt2 = 1; + }else{ + cbcr_vsd_bil_gt4 = 0; + cbcr_vsd_bil_gt2 = 0; + } + break; + case SCALE_DOWN_AVG: + cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH); + break; + default : + break; + } + break; + default : + break; + } + win->scale_cbcr_x = cbcr_xscl_factor; + win->scale_cbcr_y = cbcr_yscl_factor; + win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4; + win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2; + + DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor, + cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2); + return 0; +} + + + +static int win0_set_par(struct lcdc_device *lcdc_dev, + struct rk_screen *screen, struct rk_lcdc_win *win) +{ + u32 xact,yact,xvir, yvir,xpos, ypos; + u8 fmt_cfg = 0; + char fmt[9] = "NULL"; + + xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; + ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)){ + rk3288_lcdc_cal_scl_fac(win);/*fac,lb.gt2,gt4*/ + switch (win->format){ + case ARGB888: + fmt_cfg = 0; + win->swap_rb = 0; + break; + case XBGR888: + case ABGR888: + fmt_cfg = 0; + win->swap_rb = 1; + break; + case RGB888: + fmt_cfg = 1; + win->swap_rb = 0; + break; + case RGB565: + fmt_cfg = 2; + win->swap_rb = 0; + break; + case YUV422: + fmt_cfg = 5; + win->swap_rb = 0; + break; + case YUV420: + fmt_cfg = 4; + win->swap_rb = 0; + break; + case YUV444: + fmt_cfg = 6; + win->swap_rb = 0; + break; + default: + dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", + __func__); + break; + } + win->fmt_cfg = fmt_cfg; + win->area[0].dsp_stx = xpos; + win->area[0].dsp_sty = ypos; + xact = win->area[0].xact; + yact = win->area[0].yact; + xvir = win->area[0].xvir; + yvir = win->area[0].xvir; + } + spin_unlock(&lcdc_dev->reg_lock); + + DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" + ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, + __func__, get_format_string(win->format, fmt), xact, + yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); + return 0; + +} + +static int win1_set_par(struct lcdc_device *lcdc_dev, + struct rk_screen *screen, struct rk_lcdc_win *win) +{ + u32 xact,yact,xvir, yvir,xpos, ypos; + u8 fmt_cfg = 0; + char fmt[9] = "NULL"; + + xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len; + ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len; + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)){ + rk3288_lcdc_cal_scl_fac(win);/*fac,lb.gt2,gt4*/ + switch (win->format){ + case ARGB888: + fmt_cfg = 0; + win->swap_rb = 0; + break; + case XBGR888: + case ABGR888: + fmt_cfg = 0; + win->swap_rb = 1; + break; + case RGB888: + fmt_cfg = 1; + win->swap_rb = 0; + break; + case RGB565: + fmt_cfg = 2; + win->swap_rb = 0; + break; + case YUV422: + fmt_cfg = 5; + win->swap_rb = 0; + break; + case YUV420: + fmt_cfg = 4; + win->swap_rb = 0; + break; + case YUV444: + fmt_cfg = 6; + win->swap_rb = 0; + break; + default: + dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n", + __func__); + break; + } + win->fmt_cfg = fmt_cfg; + win->area[0].dsp_stx = xpos; + win->area[0].dsp_sty = ypos; + xact = win->area[0].xact; + yact = win->area[0].yact; + xvir = win->area[0].xvir; + yvir = win->area[0].xvir; + } + spin_unlock(&lcdc_dev->reg_lock); + + DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n" + ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, + __func__, get_format_string(win->format, fmt), xact, + yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos); + return 0; + +} + +static int win2_set_par(struct lcdc_device *lcdc_dev, + struct rk_screen *screen, struct rk_lcdc_win *win) +{ + int i; + u8 fmt_cfg; + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)){ + for(i=0;iarea_num;i++){ + switch (win->format){ + case ARGB888: + fmt_cfg = 0; + win->swap_rb = 0; + break; + case XBGR888: + case ABGR888: + fmt_cfg = 0; + win->swap_rb = 1; + break; + case RGB888: + fmt_cfg = 1; + win->swap_rb = 0; + break; + case RGB565: + fmt_cfg = 2; + win->swap_rb = 0; + break; + default: + dev_err(lcdc_dev->driver.dev, + "%s:un supported format!\n", + __func__); + break; + } + win->fmt_cfg = fmt_cfg; + win->area[i].dsp_stx = win->area[i].xpos + + screen->mode.left_margin + + screen->mode.hsync_len; + win->area[i].dsp_sty = win->area[i].ypos + + screen->mode.upper_margin + + screen->mode.vsync_len;; + } + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + +static int win3_set_par(struct lcdc_device *lcdc_dev, + struct rk_screen *screen, struct rk_lcdc_win *win) + +{ + int i; + u8 fmt_cfg; + + spin_lock(&lcdc_dev->reg_lock); + if(likely(lcdc_dev->clk_on)){ + for(i=0;iarea_num;i++){ + switch (win->format){ + case ARGB888: + fmt_cfg = 0; + win->swap_rb = 0; + break; + case XBGR888: + case ABGR888: + fmt_cfg = 0; + win->swap_rb = 1; + break; + case RGB888: + fmt_cfg = 1; + win->swap_rb = 0; + break; + case RGB565: + fmt_cfg = 2; + win->swap_rb = 0; + break; + default: + dev_err(lcdc_dev->driver.dev, + "%s:un supported format!\n", + __func__); + break; + } + win->fmt_cfg = fmt_cfg; + win->area[i].dsp_stx = win->area[i].xpos + + screen->mode.left_margin + + screen->mode.hsync_len; + win->area[i].dsp_sty = win->area[i].ypos + + screen->mode.upper_margin + + screen->mode.vsync_len;; + } + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; + + +} + +static int rk3288_set_win_par(struct rk_lcdc_driver *dev_drv, + struct rk_screen *screen, struct rk_lcdc_win *win,int win_id) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + + switch(win_id) + { + case 0: + win0_set_par(lcdc_dev, screen, win); + break; + case 1: + win1_set_par(lcdc_dev, screen, win); + break; + case 2: + win2_set_par(lcdc_dev, screen, win); + break; + case 3: + win3_set_par(lcdc_dev, screen, win); + break; + default: + dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id); + break; + } + return 0; +} +static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id) +{ + struct rk_lcdc_win *win = NULL; + struct rk_screen *screen = dev_drv->cur_screen; + int i; + + if (!screen) { + dev_err(dev_drv->dev, "screen is null!\n"); + return -ENOENT; + } + for(i=0;ilcdc_win_num;i++){ + if(dev_drv->win[i]->state == 1){ + win = dev_drv->win[i]; + rk3288_set_win_par(dev_drv,screen,win,i); + rk3288_lcdc_win_display(dev_drv,win,i); + } + } + + dev_drv->ops->ovl_mgr(dev_drv, 0, 1); + rk3288_lcdc_reg_update(dev_drv); + + + return 0; +} + +static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd, + unsigned long arg, int win_id) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct + lcdc_device, + driver); + u32 panel_size[2]; + void __user *argp = (void __user *)arg; + struct color_key_cfg clr_key_cfg; + + switch (cmd) { + case RK_FBIOGET_PANEL_SIZE: + panel_size[0] = lcdc_dev->screen->mode.xres; + panel_size[1] = lcdc_dev->screen->mode.yres; + if (copy_to_user(argp, panel_size, 8)) + return -EFAULT; + break; + case RK_FBIOPUT_COLOR_KEY_CFG: + if (copy_from_user(&clr_key_cfg, argp, + sizeof(struct color_key_cfg))) + return -EFAULT; + rk3288_lcdc_clr_key_cfg(dev_drv); + lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, + clr_key_cfg.win0_color_key_cfg); + lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, + clr_key_cfg.win1_color_key_cfg); + break; + + default: + break; + } + return 0; +} + +static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + if (dev_drv->screen0->standby) + dev_drv->screen0->standby(1); + if (dev_drv->screen_ctr_info->io_disable) + dev_drv->screen_ctr_info->io_disable(); + dev_drv->suspend_flag = 1; + flush_kthread_worker(&dev_drv->update_regs_worker); + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + rk3288_lcdc_disable_irq(lcdc_dev); + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, + v_DSP_OUT_ZERO(1)); + lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, + v_STANDBY_EN(1)); + lcdc_cfg_done(lcdc_dev); + spin_unlock(&lcdc_dev->reg_lock); + } else { + spin_unlock(&lcdc_dev->reg_lock); + return 0; + } + rk3288_lcdc_clk_disable(lcdc_dev); + return 0; +} + +static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + int i = 0; + int __iomem *c; + int v; + + if (dev_drv->screen_ctr_info->io_enable) + dev_drv->screen_ctr_info->io_enable(); + dev_drv->suspend_flag = 0; + + if (lcdc_dev->atv_layer_cnt) { + rk3288_lcdc_clk_enable(lcdc_dev); + rk3288_lcdc_reg_restore(lcdc_dev); + + spin_lock(&lcdc_dev->reg_lock); + if (dev_drv->cur_screen->dsp_lut) { + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, + v_DSP_LUT_EN(0)); + lcdc_cfg_done(lcdc_dev); + mdelay(25); + for (i = 0; i < 256; i++) { + v = dev_drv->cur_screen->dsp_lut[i]; + c = lcdc_dev->dsp_lut_addr_base + i; + writel_relaxed(v, c); + } + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, + v_DSP_LUT_EN(1)); + } + + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO, + v_DSP_OUT_ZERO(0)); + lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, + v_STANDBY_EN(0)); + lcdc_cfg_done(lcdc_dev); + + spin_unlock(&lcdc_dev->reg_lock); + } + + if (dev_drv->screen0->standby) + dev_drv->screen0->standby(0); + return 0; +} + +static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv, + int win_id, int blank_mode) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + + spin_lock(&lcdc_dev->reg_lock); + if (likely(lcdc_dev->clk_on)) { + switch (blank_mode) { + case FB_BLANK_UNBLANK: + rk3288_lcdc_early_resume(dev_drv); + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, + v_DSP_BLANK_EN(0)); + break; + case FB_BLANK_NORMAL: + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, + v_DSP_BLANK_EN(1)); + rk3288_lcdc_early_suspend(dev_drv); + break; + default: + lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN, + v_DSP_BLANK_EN(1)); + rk3288_lcdc_early_suspend(dev_drv); + break; + } + lcdc_cfg_done(lcdc_dev); + + } + spin_unlock(&lcdc_dev->reg_lock); + + dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode); + + return 0; +} + +static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id) +{ + return 0; +} + +/*overlay will be do at regupdate*/ +static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, + bool set) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + int ovl; + unsigned int mask, val; + int win0_order,win1_order,win2_order,win3_order; + win0_order = dev_drv->win[0]->z_order; + win1_order = dev_drv->win[1]->z_order; + win2_order = dev_drv->win[2]->z_order; + win3_order = dev_drv->win[3]->z_order; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on){ + if(set){ + mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL | + m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL; + val = v_DSP_LAYER0_SEL(0) | + v_DSP_LAYER1_SEL(1) | + v_DSP_LAYER2_SEL(2) | + v_DSP_LAYER3_SEL(3); + lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val); + }else{ + win0_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL); + win1_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL); + win2_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL); + win3_order = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL); + ovl = win3_order*1000 + win2_order*100 + win1_order *10 + win0_order; + } + }else{ + ovl = -EPERM; + } + spin_unlock(&lcdc_dev->reg_lock); + + return ovl; +} + +static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv, + char *buf, int win_id) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct + lcdc_device, + driver); + struct rk_screen *screen = dev_drv->cur_screen; + u16 hsync_len = screen->mode.hsync_len; + u16 left_margin = screen->mode.left_margin; + u16 vsync_len = screen->mode.vsync_len; + u16 upper_margin = screen->mode.upper_margin; + u32 fmt_id,h_pw_bp,v_pw_bp; + char format_w0[9] = "NULL"; + char format_w1[9] = "NULL"; + char format_w2[9] = "NULL"; + char format_w3[9] = "NULL"; + u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor; + u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel; + u8 w0_state,w1_state,w2_state,w3_state; + u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state; + u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state; + + u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x,w0_st_y; + u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x,w1_st_y; + u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac; + u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac; + + u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y; + u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x; + u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y; + u32 w2_0_st_x,w2_1_st_x,w2_2_st_x,w2_3_st_x; + u32 w2_0_st_y,w2_1_st_y,w2_2_st_y,w2_3_st_y; + + u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y; + u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x; + u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y; + u32 w3_0_st_x,w3_1_st_x,w3_2_st_x,w3_3_st_x; + u32 w3_0_st_y,w3_1_st_y,w3_2_st_y,w3_3_st_y; + u32 dclk_freq; + + h_pw_bp = hsync_len + left_margin; + v_pw_bp = vsync_len + upper_margin; + dclk_freq = screen->mode.pixclock; + rk3288_lcdc_reg_dump(lcdc_dev); + + spin_lock(&lcdc_dev->reg_lock); + if (lcdc_dev->clk_on) { + zorder = lcdc_readl(lcdc_dev, DSP_CTRL1); + layer0_sel = zorder & m_DSP_LAYER0_SEL; + layer1_sel = zorder & m_DSP_LAYER1_SEL; + layer2_sel = zorder & m_DSP_LAYER2_SEL; + layer3_sel = zorder & m_DSP_LAYER3_SEL; + /*WIN0*/ + win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0); + w0_state = win_ctrl & m_WIN0_EN; + fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1; + switch (fmt_id) { + case 0: + strcpy(format_w0, "ARGB888"); + break; + case 1: + strcpy(format_w0, "RGB888"); + break; + case 2: + strcpy(format_w0, "RGB565"); + break; + case 4: + strcpy(format_w0, "YCbCr420"); + break; + case 5: + strcpy(format_w0, "YCbCr422"); + break; + case 6: + strcpy(format_w0, "YCbCr444"); + break; + default: + strcpy(format_w0, "invalid\n"); + break; + } + vir_info = lcdc_readl(lcdc_dev,WIN0_VIR); + act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO); + dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO); + dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST); + y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB); + uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR); + w0_vir_y = vir_info & m_WIN0_VIR_STRIDE; + w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16; + w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1; + w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1; + w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1; + w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1; + w0_st_x = dsp_st & m_WIN0_DSP_XST; + w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16; + w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB; + w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16; + w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR; + w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16; + + /*WIN1*/ + win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0); + w1_state = win_ctrl & m_WIN1_EN; + fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1; + switch (fmt_id) { + case 0: + strcpy(format_w1, "ARGB888"); + break; + case 1: + strcpy(format_w1, "RGB888"); + break; + case 2: + strcpy(format_w1, "RGB565"); + break; + case 4: + strcpy(format_w1, "YCbCr420"); + break; + case 5: + strcpy(format_w1, "YCbCr422"); + break; + case 6: + strcpy(format_w1, "YCbCr444"); + break; + default: + strcpy(format_w1, "invalid\n"); + break; + } + vir_info = lcdc_readl(lcdc_dev,WIN1_VIR); + act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO); + dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO); + dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST); + y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB); + uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR); + w1_vir_y = vir_info & m_WIN1_VIR_STRIDE; + w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16; + w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1; + w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1; + w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1; + w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1; + w1_st_x = dsp_st & m_WIN1_DSP_XST; + w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16; + w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB; + w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16; + w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR; + w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16; + /*WIN2*/ + win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0); + w2_state = win_ctrl & m_WIN2_EN; + w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4; + w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5; + w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6; + w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7; + vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1); + w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0; + w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16; + vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3); + w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2; + w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16; + fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1; + switch (fmt_id) { + case 0: + strcpy(format_w2, "ARGB888"); + break; + case 1: + strcpy(format_w2, "RGB888"); + break; + case 2: + strcpy(format_w2, "RGB565"); + break; + case 4: + strcpy(format_w2,"8bpp"); + break; + case 5: + strcpy(format_w2,"4bpp"); + break; + case 6: + strcpy(format_w2,"2bpp"); + break; + case 7: + strcpy(format_w2,"1bpp"); + break; + default: + strcpy(format_w2, "invalid\n"); + break; + } + dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0); + dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0); + w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1; + w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1; + w2_0_st_x = dsp_st & m_WIN2_DSP_XST0; + w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0); + + dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1); + dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1); + w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1; + w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1; + w2_1_st_x = dsp_st & m_WIN2_DSP_XST1; + w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16; + + dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2); + dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2); + w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1; + w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1; + w2_2_st_x = dsp_st & m_WIN2_DSP_XST2; + w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16; + + dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3); + dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3); + w2_3_dsp_x = dsp_info & m_WIN2_DSP_WIDTH3+1; + w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1; + w2_3_st_x = dsp_st & m_WIN2_DSP_XST3; + w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16; + + /*WIN3*/ + win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0); + w3_state = win_ctrl & m_WIN3_EN; + w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4; + w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5; + w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6; + w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7; + vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1); + w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0; + w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16; + vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3); + w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2; + w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16; + fmt_id = (win_ctrl | m_WIN3_DATA_FMT)>>1; + switch (fmt_id) { + case 0: + strcpy(format_w3, "ARGB888"); + break; + case 1: + strcpy(format_w3, "RGB888"); + break; + case 2: + strcpy(format_w3, "RGB565"); + break; + case 4: + strcpy(format_w3,"8bpp"); + break; + case 5: + strcpy(format_w3,"4bpp"); + break; + case 6: + strcpy(format_w3,"2bpp"); + break; + case 7: + strcpy(format_w3,"1bpp"); + break; + default: + strcpy(format_w3, "invalid"); + break; + } + dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0); + dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0); + w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1; + w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1; + w3_0_st_x = dsp_st & m_WIN3_DSP_XST0; + w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16; + + dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1); + dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1); + w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1; + w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1; + w3_1_st_x = dsp_st & m_WIN3_DSP_XST1; + w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16; + + dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2); + dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2); + w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1; + w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1; + w3_2_st_x = dsp_st & m_WIN3_DSP_XST2; + w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16; + + dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3); + dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3); + w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1; + w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1; + w3_3_st_x = dsp_st & m_WIN3_DSP_XST3; + w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16; + + } else { + spin_unlock(&lcdc_dev->reg_lock); + return -EPERM; + } + spin_unlock(&lcdc_dev->reg_lock); + return snprintf(buf, PAGE_SIZE, + "h:pw+bp=%d\n" + "v:pw+bp=%d\n" + "z-order:\n" + " layer3_sel_win[%d]\n" + " layer2_sel_win[%d]\n" + " layer1_sel_win[%d]\n" + " layer0_sel_win[%d]\n" + "win0:\n" + " state:%d\n" + " fmt:%s\n" + " y_vir:%d\n" + " uv_vir:%d\n" + " xact:%d\n" + " yact:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " y_h_fac:%d\n" + " y_v_fac:%d\n" + " uv_h_fac:%d\n" + " uv_v_fac:%d\n" + " y_addr: 0x%x\n" + " uv_addr:0x%x\n" + "win1:\n" + " state:%d\n" + " fmt:%s\n" + " y_vir:%d\n" + " uv_vir:%d\n" + " xact:%d\n" + " yact:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " y_h_fac:%d\n" + " y_v_fac:%d\n" + " uv_h_fac:%d\n" + " uv_v_fac:%d\n" + " y_addr: 0x%x\n" + " uv_addr:0x%x\n" + "win2:\n" + " state:%d\n" + " fmt:%s\n" + " area0:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + " area1:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + " area2:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + " area3:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + "win3:\n" + " state:%d\n" + " fmt:%s\n" + " area0:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + " area1:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " area2:\n" + " addr:0x%x\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n" + " area3:\n" + " state:%d\n" + " y_vir:%d\n" + " dsp_x:%d\n" + " dsp_y:%d\n" + " x_st:%d\n" + " y_st:%d\n" + " addr:0x%x\n", + h_pw_bp,v_pw_bp, + layer3_sel,layer2_sel,layer1_sel,layer0_sel, + w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y, + w0_dsp_x,w0_dsp_y,w0_st_x,w0_st_y,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac, + w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST), + lcdc_readl(lcdc_dev, WIN0_CBR_MST), + + w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y, + w1_dsp_x,w1_dsp_y,w1_st_x,w1_st_y,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac, + w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST), + lcdc_readl(lcdc_dev, WIN1_CBR_MST), + + w2_state,format_w2, + w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y, + w2_0_st_x,w2_0_st_y,lcdc_readl(lcdc_dev, WIN2_MST0), + + w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y, + w2_1_st_x,w2_1_st_y,lcdc_readl(lcdc_dev, WIN2_MST1), + + w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y, + w2_2_st_x,w2_2_st_y,lcdc_readl(lcdc_dev, WIN2_MST2), + + w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y, + w2_3_st_x,w2_3_st_y,lcdc_readl(lcdc_dev, WIN2_MST3), + + w3_state,format_w3, + w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y, + w3_0_st_x,w3_0_st_y,lcdc_readl(lcdc_dev, WIN3_MST0), + + w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y, + w3_1_st_x,w3_1_st_y,lcdc_readl(lcdc_dev, WIN3_MST1), + + w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y, + w3_2_st_x,w3_2_st_y,lcdc_readl(lcdc_dev, WIN3_MST2), + + w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y, + w3_3_st_x,w3_3_st_y,lcdc_readl(lcdc_dev, WIN3_MST3) + ); + +} + +static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, + bool set) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_screen *screen = dev_drv->cur_screen; + u64 ft = 0; + u32 dotclk; + int ret; + u32 pixclock; + u32 x_total, y_total; + if (set) { + ft = div_u64(1000000000000llu, fps); + x_total = + screen->mode.upper_margin + screen->mode.lower_margin + + screen->mode.yres + screen->mode.vsync_len; + y_total = + screen->mode.left_margin + screen->mode.right_margin + + screen->mode.xres + screen->mode.hsync_len; + dev_drv->pixclock = div_u64(ft, x_total * y_total); + dotclk = div_u64(1000000000000llu, dev_drv->pixclock); + ret = clk_set_rate(lcdc_dev->dclk, dotclk); + } + + pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk)); + dev_drv->pixclock = lcdc_dev->pixclock = pixclock; + fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock); + screen->ft = 1000 / fps; /*one frame time in ms */ + + if (set) + dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__, + clk_get_rate(lcdc_dev->dclk), fps); + + return fps; +} + +static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, + enum fb_win_map_order order) +{ + mutex_lock(&dev_drv->fb_win_id_mutex); + if (order == FB_DEFAULT_ORDER) + order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3; + dev_drv->fb3_win_id = order / 1000; + dev_drv->fb2_win_id = (order / 100) % 10; + dev_drv->fb1_win_id = (order / 10) % 10; + dev_drv->fb0_win_id = order % 10; + mutex_unlock(&dev_drv->fb_win_id_mutex); + + return 0; +} + +static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv, + const char *id) +{ + int win_id = 0; + mutex_lock(&dev_drv->fb_win_id_mutex); + if (!strcmp(id, "fb0") || !strcmp(id, "fb4")) + win_id = dev_drv->fb0_win_id; + else if (!strcmp(id, "fb1") || !strcmp(id, "fb5")) + win_id = dev_drv->fb1_win_id; + else if (!strcmp(id, "fb2") || !strcmp(id, "fb6")) + win_id = dev_drv->fb2_win_id; + else if (!strcmp(id, "fb3") || !strcmp(id, "fb7")) + win_id = dev_drv->fb3_win_id; + mutex_unlock(&dev_drv->fb_win_id_mutex); + + return win_id; +} + +static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut) +{ + int i = 0; + int __iomem *c; + int v; + int ret = 0; + + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0)); + lcdc_cfg_done(lcdc_dev); + msleep(25); + if (dev_drv->cur_screen->dsp_lut) { + for (i = 0; i < 256; i++) { + v = dev_drv->cur_screen->dsp_lut[i] = lut[i]; + c = lcdc_dev->dsp_lut_addr_base + i; + writel_relaxed(v, c); + + } + } else { + dev_err(dev_drv->dev, "no buffer to backup lut data!\n"); + ret = -1; + } + lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1)); + lcdc_cfg_done(lcdc_dev); + + return ret; +} + +static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN, + v_DIRECT_PATH_EN(open)); + lcdc_cfg_done(lcdc_dev); + return 0; +} + +static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id) +{ + struct lcdc_device *lcdc_dev = container_of(dev_drv, + struct lcdc_device, driver); + lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL, + v_DIRECT_PATCH_SEL(win_id)); + lcdc_cfg_done(lcdc_dev); + return 0; + +} + +static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + int ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN); + return ovl; +} + +int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + u32 int_reg; + int ret; + + if (lcdc_dev->clk_on) { + int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); + if (int_reg & m_LINE_FLAG_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, + v_LINE_FLAG_INTR_CLR(1)); + ret = RK_LF_STATUS_FC; + } else + ret = RK_LF_STATUS_FR; + } else { + ret = RK_LF_STATUS_NC; + } + + return ret; +} +static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,unsigned int *dsp_addr) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + + if(lcdc_dev->clk_on){ + dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST); + dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST); + dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0); + dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0); + } + return 0; +} + +static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,int mode) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + struct rk_screen *screen = dev_drv->cur_screen; + int total_pixel,calc_pixel,stage_up,stage_down; + u32 mask, val; + + u32 cabc_mode[5][3]={ + /*num ,up, down*/ + {2, 10, 10}, /*mode 1*/ + {4, 10, 10}, /*mode 2*/ + {6, 10, 10}, /*mode 3*/ + {8, 10, 10}, /*mode 4*/ + {10, 10, 10}, /*mode 5*/ + }; + /*iomux connect to vop or pwm*/ + if(mode == 0){ + DBG(3,"close cabc\n"); + mask = m_CABC_EN; + val = v_CABC_EN(0); + lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); + return 0; + } + total_pixel = screen->mode.xres * screen->mode.yres; + calc_pixel = total_pixel * (100 - cabc_mode[mode-1][0])/100; + stage_up = cabc_mode[mode-1][1]; + stage_down = cabc_mode[mode-1][2]; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on){ + mask = m_CABC_TOTAL_NUM | m_CABC_STAGE_DOWN; + val = v_CABC_TOTAL_NUM(total_pixel) | v_CABC_STAGE_DOWN(stage_down); + lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val); + + mask = m_CABC_EN | m_CABC_CALC_PIXEL_NUM | + m_CABC_STAGE_UP; + val = v_CABC_EN(1) | v_CABC_CALC_PIXEL_NUM(calc_pixel) | + v_CABC_STAGE_UP(stage_up); + lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val); + lcdc_cfg_done(lcdc_dev); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} +/* + Sin0=*0.000???????? Cos0=*1.000 + Sin5=*0.087???????C Cos5=*0.996 + Sin10=*0.174 Cos10=*0.985 + Sin15=*0.259 ???????CCos15=*0.966 + Sin20=*0.342????????Cos20=*0.940 + Sin25=*0.422????????Cos25=*0.906 + Sin30=*0.500????????Cos30=*0.866 +*/ +static int rk3288_lcdc_set_hue(struct rk_lcdc_driver *dev_drv,int hue) +{ + + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + int sin_hue_val,cos_hue_val; + u32 mask, val; + + int sin_hue[7]={0,22, 44, 66, 87, 108, 128}; + int cos_hue[7]={256,254,252,247,240,231,221}; + + if((hue > 0)&&(hue <= 30)){ + /*sin_hue_val = (int)sin_hue[hue] * 256; + cos_hue_val = (int)cos_hue[hue] * 256;*/ + hue /= 5; + sin_hue_val = sin_hue[hue]; + cos_hue_val = cos_hue[hue]; + }else if((hue > 30)&&(hue <= 60)){ + hue -= 30; + hue /= 5; + /*sin_hue_val = (int)sin_hue[hue] * 256 + 0x100; + cos_hue_val = (int)cos_hue[hue] * 256 + 0x100;*/ + sin_hue_val = sin_hue[hue] + 0x100; + cos_hue_val = cos_hue[hue] + 0x100; + }else{ + dev_warn(lcdc_dev->dev,"hue=%d should be [0:60]\n",hue); + } + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on){ + + mask = m_BCSH_OUT_MODE; + val = v_BCSH_OUT_MODE(3); + lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); + + mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE; + val = v_BCSH_SIN_HUE(sin_hue_val) | v_BCSH_COS_HUE(cos_hue_val); + lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val); + + mask = m_BCSH_EN; + val = v_BCSH_EN(1); + lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); + lcdc_cfg_done(lcdc_dev); + } + spin_unlock(&lcdc_dev->reg_lock); + + return 0; +} + +static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,int bri,int con,int sat) +{ + struct lcdc_device *lcdc_dev = + container_of(dev_drv, struct lcdc_device, driver); + u32 mask, val; + + spin_lock(&lcdc_dev->reg_lock); + if(lcdc_dev->clk_on){ + mask = m_BCSH_OUT_MODE | m_BCSH_BRIGHTNESS | + m_BCSH_CONTRAST | m_BCSH_SAT_CON; + val = v_BCSH_OUT_MODE(3) | v_BCSH_BRIGHTNESS(bri) | + v_BCSH_CONTRAST(con) | v_BCSH_SAT_CON(sat); + lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val); + + mask = m_BCSH_EN; + val = v_BCSH_EN(1); + lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val); + lcdc_cfg_done(lcdc_dev); + } + spin_unlock(&lcdc_dev->reg_lock); + return 0; +} + + +static struct rk_lcdc_win lcdc_win[] = { + [0] = { + .name = "win0", + .id = 0, + .support_3d = false, + }, + [1] = { + .name = "win1", + .id = 1, + .support_3d = false, + }, + [2] = { + .name = "win2", + .id = 2, + .support_3d = false, + }, + [3] = { + .name = "win3", + .id = 3, + .support_3d = false, + }, +}; + +static struct rk_lcdc_drv_ops lcdc_drv_ops = { + .open = rk3288_lcdc_open, + .load_screen = rk3288_load_screen, + .set_par = rk3288_lcdc_set_par, + .pan_display = rk3288_lcdc_pan_display, + .lcdc_reg_update = rk3288_lcdc_reg_update, + .blank = rk3288_lcdc_blank, + .ioctl = rk3288_lcdc_ioctl, + .suspend = rk3288_lcdc_early_suspend, + .resume = rk3288_lcdc_early_resume, + .get_win_state = rk3288_lcdc_get_win_state, + .ovl_mgr = rk3288_lcdc_ovl_mgr, + .get_disp_info = rk3288_lcdc_get_disp_info, + .fps_mgr = rk3288_lcdc_fps_mgr, + .fb_get_win_id = rk3288_lcdc_get_win_id, + .fb_win_remap = rk3288_fb_win_remap, + .set_dsp_lut = rk3288_set_dsp_lut, + .poll_vblank = rk3288_lcdc_poll_vblank, + .dpi_open = rk3288_lcdc_dpi_open, + .dpi_win_sel = rk3288_lcdc_dpi_win_sel, + .dpi_status = rk3288_lcdc_dpi_status, + .get_dsp_addr = rk3288_lcdc_get_dsp_addr, + .set_dsp_cabc = rk3288_lcdc_set_dsp_cabc, + .set_dsp_hue = rk3288_lcdc_set_hue, + .set_dsp_bcsh_bcs = rk3288_lcdc_set_bcsh_bcs, +}; +static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val) +{ + if (reg_val & m_WIN0_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR, + v_WIN0_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"win0 empty irq!"); + }else if (reg_val & m_WIN1_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR, + v_WIN1_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"win1 empty irq!"); + }else if (reg_val & m_WIN2_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR, + v_WIN2_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"win2 empty irq!"); + }else if (reg_val & m_WIN3_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR, + v_WIN3_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"win3 empty irq!"); + }else if (reg_val & m_HWC_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR, + v_HWC_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"HWC empty irq!"); + }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR, + v_POST_BUF_EMPTY_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"post buf empty irq!"); + }else if (reg_val & m_PWM_GEN_INTR_STS) { + lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR, + v_PWM_GEN_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"PWM gen irq!"); + } + + return 0; +} +static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id) +{ + struct lcdc_device *lcdc_dev = + (struct lcdc_device *)dev_id; + ktime_t timestamp = ktime_get(); + u32 intr0_reg; + intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0); + + if(intr0_reg & m_FS_INTR_STS){ + timestamp = ktime_get(); + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR, + v_FS_INTR_CLR(1)); + if(lcdc_dev->driver.wait_fs){ + spin_lock(&(lcdc_dev->driver.cpl_lock)); + complete(&(lcdc_dev->driver.frame_done)); + spin_unlock(&(lcdc_dev->driver.cpl_lock)); + } + lcdc_dev->driver.vsync_info.timestamp = timestamp; + wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait); + + }else if(intr0_reg & m_LINE_FLAG_INTR_STS){ + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR, + v_LINE_FLAG_INTR_CLR(1)); + }else if(intr0_reg & m_BUS_ERROR_INTR_STS){ + lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR, + v_BUS_ERROR_INTR_CLR(1)); + dev_warn(lcdc_dev->dev,"buf_error_int!"); + } + + /*for debug*/ + #if 0 + intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1); + if(intr1_reg != 0){ + rk3288_lcdc_parse_irq(intr1_reg); + } + #endif + return IRQ_HANDLED; +} + +#if defined(CONFIG_PM) +static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int rk3288_lcdc_resume(struct platform_device *pdev) +{ + return 0; +} +#else +#define rk3288_lcdc_suspend NULL +#define rk3288_lcdc_resume NULL +#endif + +static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev) +{ + struct device_node *np = lcdc_dev->dev->of_node; + int val; + if (of_property_read_u32(np, "rockchip,prop", &val)) + lcdc_dev->prop = PRMRY; /*default set it as primary */ + else + lcdc_dev->prop = val; + + if (of_property_read_u32(np, "rockchip,pwr18", &val)) + lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */ + else + lcdc_dev->pwr18 = (val ? true : false); + return 0; +} + +static int rk3288_lcdc_probe(struct platform_device *pdev) +{ + struct lcdc_device *lcdc_dev = NULL; + struct rk_lcdc_driver *dev_drv; + struct device *dev = &pdev->dev; + struct resource *res; + struct device_node *np = pdev->dev.of_node; + int prop; + int ret = 0; + + /*if the primary lcdc has not registered ,the extend + lcdc register later */ + of_property_read_u32(np, "rockchip,prop", &prop); + if (prop == EXTEND) { + if (!is_prmry_rk_lcdc_registered()) + return -EPROBE_DEFER; + } + lcdc_dev = devm_kzalloc(dev, + sizeof(struct lcdc_device), GFP_KERNEL); + if (!lcdc_dev) { + dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!"); + return -ENOMEM; + } + platform_set_drvdata(pdev, lcdc_dev); + lcdc_dev->dev = dev; + rk3288_lcdc_parse_dt(lcdc_dev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + lcdc_dev->reg_phy_base = res->start; + lcdc_dev->len = resource_size(res); + lcdc_dev->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(lcdc_dev->regs)) + return PTR_ERR(lcdc_dev->regs); + + lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL); + if (IS_ERR(lcdc_dev->regsbak)) + return PTR_ERR(lcdc_dev->regsbak); + lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR); + lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base); + if (lcdc_dev->id < 0) { + dev_err(&pdev->dev, "no such lcdc device!\n"); + return -ENXIO; + } + dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id); + dev_drv = &lcdc_dev->driver; + dev_drv->dev = dev; + dev_drv->prop = prop; + dev_drv->id = lcdc_dev->id; + dev_drv->ops = &lcdc_drv_ops; + dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win); + spin_lock_init(&lcdc_dev->reg_lock); + + lcdc_dev->irq = platform_get_irq(pdev, 0); + if (lcdc_dev->irq < 0) { + dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n", + lcdc_dev->id); + return -ENXIO; + } + + ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr, + IRQF_DISABLED, dev_name(dev), lcdc_dev); + if (ret) { + dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", + lcdc_dev->irq, ret); + return ret; + } + + ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id); + if (ret < 0) { + dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id); + return ret; + } + lcdc_dev->screen = dev_drv->screen0; + + dev_info(dev, "lcdc%d probe ok\n", lcdc_dev->id); + + return 0; +} + +static int rk3288_lcdc_remove(struct platform_device *pdev) +{ + + return 0; +} + +static void rk3288_lcdc_shutdown(struct platform_device *pdev) +{ + struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev); + + rk3288_lcdc_deint(lcdc_dev); + rk_disp_pwr_disable(&lcdc_dev->driver); +} + +#if defined(CONFIG_OF) +static const struct of_device_id rk3288_lcdc_dt_ids[] = { + {.compatible = "rockchip,rk3288-lcdc",}, + {} +}; +#endif + +static struct platform_driver rk3288_lcdc_driver = { + .probe = rk3288_lcdc_probe, + .remove = rk3288_lcdc_remove, + .driver = { + .name = "rk3288-lcdc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids), + }, + .suspend = rk3288_lcdc_suspend, + .resume = rk3288_lcdc_resume, + .shutdown = rk3288_lcdc_shutdown, +}; + +static int __init rk3288_lcdc_module_init(void) +{ + return platform_driver_register(&rk3288_lcdc_driver); +} + +static void __exit rk3288_lcdc_module_exit(void) +{ + platform_driver_unregister(&rk3288_lcdc_driver); +} + +fs_initcall(rk3288_lcdc_module_init); +module_exit(rk3288_lcdc_module_exit); + + diff --git a/drivers/video/rockchip/lcdc/rk3288_lcdc.h b/drivers/video/rockchip/lcdc/rk3288_lcdc.h index ceb8cbba0731..1ca61fe63e3d 100755 --- a/drivers/video/rockchip/lcdc/rk3288_lcdc.h +++ b/drivers/video/rockchip/lcdc/rk3288_lcdc.h @@ -1,1587 +1,1508 @@ -#ifndef RK3288_LCDC_H_ -#define RK3288_LCDC_H_ - -#include -#include -#include - - -/*******************register definition**********************/ - -#define REG_CFG_DONE (0x0000) -#define VERSION_INFO (0x0004) -#define m_RTL_VERSION (0xffff<<0) -#define m_FPGA_VERSION (0xffff<<16) -#define SYS_CTRL (0x0008) -#define v_DIRECT_PATH_EN(x) (((x)&1)<<0) -#define v_DIRECT_PATCH_SEL(x) (((x)&3)<<1) -#define v_DOUB_CHANNEL_EN(x) (((x)&1)<<3) -#define v_DOUB_CH_OVERLAP_NUM(x) (((x)&0xf)<<4) -#define v_EDPI_HALT_EN(x) (((x)&1)<<8) -#define v_EDPI_WMS_MODE(x) (((x)&1)<<9) -#define v_EDPI_WMS_FS(x) (((x)&1)<<10) -#define v_RGB_OUT_EN(x) (((x)&1)<<12) -#define v_HDMI_OUT_EN(x) (((x)&1)<<13) -#define v_EDP_OUT_EN(x) (((x)&1)<<14) -#define v_MIPI_OUT_EN(x) (((x)&1)<<15) -#define v_DMA_BURST_LENGTH(x) (((x)&3)<<18) -#define v_MMU_EN(x) (((x)&1)<<20) -#define v_DMA_STOP(x) (((x)&1)<<21) -#define v_STANDBY_EN(x) (((x)&1)<<22) -#define v_AUTO_GATING_EN(x) (((x)&1)<<23) - -#define m_DIRECT_PATH_EN (1<<0) -#define m_DIRECT_PATCH_SEL (3<<1) -#define m_DOUB_CHANNEL_EN (1<<3) -#define m_DOUB_CH_OVERLAP_NUM (0xf<<4) -#define m_EDPI_HALT_EN (1<<8) -#define m_EDPI_WMS_MODE (1<<9) -#define m_EDPI_WMS_FS (1<<10) -#define m_RGB_OUT_EN (1<<12) -#define m_HDMI_OUT_EN (1<<13) -#define m_EDP_OUT_EN (1<<14) -#define m_MIPI_OUT_EN (1<<15) -#define m_DMA_BURST_LENGTH (3<<18) -#define m_MMU_EN (1<<20) -#define m_DMA_STOP (1<<21) -#define m_STANDBY_EN (1<<22) -#define m_AUTO_GATING_EN (1<<23) -#define SYS_CTRL1 (0x000c) -#define v_NOC_HURRY_EN(x) (((x)&0x1 )<<0 ) -#define v_NOC_HURRY_VALUE(x) (((x)&0x3 )<<1 ) -#define v_NOC_HURRY_THRESHOLD(x) (((x)&0x3f)<<3 ) -#define v_NOC_QOS_EN(x) (((x)&0x1 )<<9 ) -#define v_NOC_WIN_QOS(x) (((x)&0x3 )<<10) -#define v_AXI_MAX_OUTSTANDING_EN(x) (((x)&0x1 )<<12) -#define v_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<13) - -#define m_NOC_HURRY_EN (0x1 <<0 ) -#define m_NOC_HURRY_VALUE (0x3 <<1 ) -#define m_NOC_HURRY_THRESHOLD (0x3f<<3 ) -#define m_NOC_QOS_EN (0x1 <<9 ) -#define m_NOC_WIN_QOS (0x3 <<10) -#define m_AXI_MAX_OUTSTANDING_EN (0x1 <<12) -#define m_AXI_OUTSTANDING_MAX_NUM (0x1f<<13) -// -#define DSP_CTRL0 (0x0010) -#define v_DSP_OUT_MODE(x) (((x)&0x0f)<<0) -#define v_DSP_HSYNC_POL(x) (((x)&1)<<4) -#define v_DSP_VSYNC_POL(x) (((x)&1)<<5) -#define v_DSP_DEN_POL(x) (((x)&1)<<6) -#define v_DSP_DCLK_POL(x) (((x)&1)<<7) -#define v_DSP_DCLK_DDR(x) (((x)&1)<<8) -#define v_DSP_DDR_PHASE(x) (((x)&1)<<9) -#define v_DSP_INTERLACE(x) (((x)&1)<<10) -#define v_DSP_FIELD_POL(x) (((x)&1)<<11) -#define v_DSP_BG_SWAP(x) (((x)&1)<<12) -#define v_DSP_RB_SWAP(x) (((x)&1)<<13) -#define v_DSP_RG_SWAP(x) (((x)&1)<<14) -#define v_DSP_DELTA_SWAP(x) (((x)&1)<<15) -#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<16) -#define v_DSP_OUT_ZERO(x) (((x)&1)<<17) -#define v_DSP_BLANK_EN(x) (((x)&1)<<18) -#define v_DSP_BLACK_EN(x) (((x)&1)<<19) -#define v_DSP_CCIR656_AVG(x) (((x)&1)<<20) -#define v_DSP_YUV_CLIP(x) (((x)&1)<<21) -#define v_DSP_X_MIR_EN(x) (((x)&1)<<22) -#define v_DSP_Y_MIR_EN(x) (((x)&1)<<23) -#define m_DSP_OUT_MODE (0x0f<<0) -#define m_DSP_HSYNC_POL (1<<4) -#define m_DSP_VSYNC_POL (1<<5) -#define m_DSP_DEN_POL (1<<6) -#define m_DSP_DCLK_POL (1<<7) -#define m_DSP_DCLK_DDR (1<<8) -#define m_DSP_DDR_PHASE (1<<9) -#define m_DSP_INTERLACE (1<<10) -#define m_DSP_FIELD_POL (1<<11) -#define m_DSP_BG_SWAP (1<<12) -#define m_DSP_RB_SWAP (1<<13) -#define m_DSP_RG_SWAP (1<<14) -#define m_DSP_DELTA_SWAP (1<<15) -#define m_DSP_DUMMY_SWAP (1<<16) -#define m_DSP_OUT_ZERO (1<<17) -#define m_DSP_BLANK_EN (1<<18) -#define m_DSP_BLACK_EN (1<<19) -#define m_DSP_CCIR656_AVG (1<<20) -#define m_DSP_YUV_CLIP (1<<21) -#define m_DSP_X_MIR_EN (1<<22) -#define m_DSP_Y_MIR_EN (1<<23) - -#define DSP_CTRL1 (0x0014) -#define v_DSP_LUT_EN(x) (((x)&1)<<0) -#define v_PRE_DITHER_DOWN_EN(x) (((x)&1)<<1) -#define v_DITHER_DOWN_EN(x) (((x)&1)<<2) -#define v_DITHER_DOWN_MODE(x) (((x)&1)<<3) -#define v_DITHER_DOWN_SEL(x) (((x)&1)<<4) -#define v_DITHER_UP_EN(x) (((x)&1)<<6) -#define v_DSP_LAYER0_SEL(x) (((x)&3)<<8) -#define v_DSP_LAYER1_SEL(x) (((x)&3)<<10) -#define v_DSP_LAYER2_SEL(x) (((x)&3)<<12) -#define v_DSP_LAYER3_SEL(x) (((x)&3)<<14) -#define m_DSP_LUT_EN (1<<0) -#define m_PRE_DITHER_DOWN_EN (1<<1) -#define m_DITHER_DOWN_EN (1<<2) -#define m_DITHER_DOWN_MODE (1<<3) -#define m_DITHER_DOWN_SEL (1<<4) -#define m_DITHER_UP_EN (1<<6) -#define m_DSP_LAYER0_SEL (3<<8) -#define m_DSP_LAYER1_SEL (3<<10) -#define m_DSP_LAYER2_SEL (3<<12) -#define m_DSP_LAYER3_SEL (3<<16) - -#define DSP_BG (0x0018) -#define v_DSP_BG_BLUE(x) (((x)&0x3ff)<<0) -#define v_DSP_BG_GREEN(x) (((x)&0x3ff)<<10) -#define v_DSP_BG_RED(x) (((x)&0x3ff)<<20) -#define m_DSP_BG_BLUE (0x3ff<<0) -#define m_DSP_BG_GREEN (0x3ff<<10) -#define m_DSP_BG_RED (0x3ff<<20) - -#define MCU_CTRL (0x001c) -#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0) -#define v_MCU_CS_PST(x) (((x)&0xf)<<6) -#define v_MCU_CS_PEND(x) (((x)&0x3f)<<10) -#define v_MCU_RW_PST(x) (((x)&0xf)<<16) -#define v_MCU_RW_PEND(x) (((x)&0x3f)<<20) -#define v_MCU_CLK_SEL(x) (((x)&1)<<26) -#define v_MCU_HOLD_MODE(x) (((x)&1)<<27) -#define v_MCU_FRAME_ST(x) (((x)&1)<<28) -#define v_MCU_RS(x) (((x)&1)<<29) -#define v_MCU_BYPASS(x) (((x)&1)<<30) -#define v_MCU_TYPE(x) (((x)&1)<<31) -#define m_MCU_PIX_TOTAL (0x3f<<0) -#define m_MCU_CS_PST (0xf<<6) -#define m_MCU_CS_PEND (0x3f<<10) -#define m_MCU_RW_PST (0xf<<16) -#define m_MCU_RW_PEND (0x3f<<20) -#define m_MCU_CLK_SEL (1<<26) -#define m_MCU_HOLD_MODE (1<<27) -#define m_MCU_FRAME_ST (1<<28) -#define m_MCU_RS (1<<29) -#define m_MCU_BYPASS (1<<30) -#define m_MCU_TYPE ((u32)1<<31) - -#define INTR_CTRL0 (0x0020) -#define v_DSP_HOLD_VALID_INTR_STS(x) (((x)&1)<<0) -#define v_FS_INTR_STS(x) (((x)&1)<<1) -#define v_LINE_FLAG_INTR_STS(x) (((x)&1)<<2) -#define v_BUS_ERROR_INTR_STS(x) (((x)&1)<<3) -#define v_DSP_HOLD_VALID_INTR_EN(x) (((x)&1)<<4) -#define v_FS_INTR_EN(x) (((x)&1)<<5) -#define v_LINE_FLAG_INTR_EN(x) (((x)&1)<<6) -#define v_BUS_ERROR_INTR_EN(x) (((x)&1)<<7) -#define v_DSP_HOLD_VALID_INTR_CLR(x) (((x)&1)<<8) -#define v_FS_INTR_CLR(x) (((x)&1)<<9) -#define v_LINE_FLAG_INTR_CLR(x) (((x)&1)<<10) -#define v_BUS_ERROR_INTR_CLR(x) (((x)&1)<<11) -#define v_DSP_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) - -#define m_DSP_HOLD_VALID_INTR_STS (1<<0) -#define m_FS_INTR_STS (1<<1) -#define m_LINE_FLAG_INTR_STS (1<<2) -#define m_BUS_ERROR_INTR_STS (1<<3) -#define m_DSP_HOLD_VALID_INTR_EN (1<<4) -#define m_FS_INTR_EN (1<<5) -#define m_LINE_FLAG_INTR_EN (1<<6) -#define m_BUS_ERROR_INTR_EN (1<<7) -#define m_DSP_HOLD_VALID_INTR_CLR (1<<8) -#define m_FS_INTR_CLR (1<<9) -#define m_LINE_FLAG_INTR_CLR (1<<10) -#define m_BUS_ERROR_INTR_CLR (1<<11) -#define m_DSP_LINE_FLAG_NUM (0xfff<<12) - -#define INTR_CTRL1 (0x0024) -#define v_WIN0_EMPTY_INTR_STS(x) (((x)&1)<<0) -#define v_WIN1_EMPTY_INTR_STS(x) (((x)&1)<<1) -#define v_WIN2_EMPTY_INTR_STS(x) (((x)&1)<<2) -#define v_WIN3_EMPTY_INTR_STS(x) (((x)&1)<<3) -#define v_HWC_EMPTY_INTR_STS(x) (((x)&1)<<4) -#define v_POST_BUF_EMPTY_INTR_STS(x) (((x)&1)<<5) -#define v_PWM_GEN_INTR_STS(x) (((x)&1)<<6) -//bit[7] reserved -#define v_WIN0_EMPTY_INTR_EN(x) (((x)&1)<<8) -#define v_WIN1_EMPTY_INTR_EN(x) (((x)&1)<<9) -#define v_WIN2_EMPTY_INTR_EN(x) (((x)&1)<<10) -#define v_WIN3_EMPTY_INTR_EN(x) (((x)&1)<<11) -#define v_HWC_EMPTY_INTR_EN(x) (((x)&1)<<12) -#define v_POST_BUF_EMPTY_INTR_EN(x) (((x)&1)<<13) -#define v_PWM_GEN_INTR_EN(x) (((x)&1)<<14) -//bit[15] reserved -#define v_WIN0_EMPTY_INTR_CLR(x) (((x)&1)<<16) -#define v_WIN1_EMPTY_INTR_CLR(x) (((x)&1)<<17) -#define v_WIN2_EMPTY_INTR_CLR(x) (((x)&1)<<18) -#define v_WIN3_EMPTY_INTR_CLR(x) (((x)&1)<<19) -#define v_HWC_EMPTY_INTR_CLR(x) (((x)&1)<<20) -#define v_POST_BUF_EMPTY_INTR_CLR(x) (((x)&1)<<21) -#define v_PWM_GEN_INTR_CLR(x) (((x)&1)<<22) - -#define m_WIN0_EMPTY_INTR_STS (1<<0) -#define m_WIN1_EMPTY_INTR_STS (1<<1) -#define m_WIN2_EMPTY_INTR_STS (1<<2) -#define m_WIN3_EMPTY_INTR_STS (1<<3) -#define m_HWC_EMPTY_INTR_STS (1<<4) -#define m_POST_BUF_EMPTY_INTR_STS (1<<5) -#define m_PWM_GEN_INTR_STS (1<<6) -//bit[7] reserved -#define m_WIN0_EMPTY_INTR_EN (1<<8) -#define m_WIN1_EMPTY_INTR_EN (1<<9) -#define m_WIN2_EMPTY_INTR_EN (1<<10) -#define m_WIN3_EMPTY_INTR_EN (1<<11) -#define m_HWC_EMPTY_INTR_EN (1<<12) -#define m_POST_BUF_EMPTY_INTR_EN (1<<13) -#define m_PWM_GEN_INTR_EN (1<<14) -//bit[15] reserved -#define m_WIN0_EMPTY_INTR_CLR (1<<16) -#define m_WIN1_EMPTY_INTR_CLR (1<<17) -#define m_WIN2_EMPTY_INTR_CLR (1<<18) -#define m_WIN3_EMPTY_INTR_CLR (1<<19) -#define m_HWC_EMPTY_INTR_CLR (1<<20) -#define m_POST_BUF_EMPTY_INTR_CLR (1<<21) -#define m_PWM_GEN_INTR_CLR (1<<22) - -//#define INTR_RESERVED0 (0x0028) -//#define INTR_RESERVED1 (0x002c) - -//win0 register -#define WIN0_CTRL0 (0x0030) -#define v_WIN0_EN(x) (((x)&1)<<0) -#define v_WIN0_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN0_FMT_10(x) (((x)&1)<<4) -#define v_WIN0_LB_MODE(x) (((x)&7)<<5) -#define v_WIN0_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN0_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN0_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN0_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN0_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN0_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN0_PPAS_ZERO_EN(x) (((x)&1)<<16) -#define v_WIN0_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN0_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN0_YUV_CLIP(x) (((x)&1)<<20) - -#define m_WIN0_EN (1<<0) -#define m_WIN0_DATA_FMT (7<<1) -#define m_WIN0_FMT_10 (1<<4) -#define m_WIN0_LB_MODE (3<<5) -#define m_WIN0_INTERLACE_READ (1<<8) -#define m_WIN0_NO_OUTSTANDING (1<<9) -#define m_WIN0_CSC_MODE (3<<10) -#define m_WIN0_RB_SWAP (1<<12) -#define m_WIN0_ALPHA_SWAP (1<<13) -#define m_WIN0_MID_SWAP (1<<14) -#define m_WIN0_UV_SWAP (1<<15) -#define m_WIN0_PPAS_ZERO_EN (1<<16) -#define m_WIN0_YRGB_DEFLICK (1<<18) -#define m_WIN0_CBR_DEFLICK (1<<19) -#define m_WIN0_YUV_CLIP (1<<20) - - -#define WIN0_CTRL1 (0x0034) -#define v_WIN0_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN0_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN0_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN0_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN0_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN0_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN0_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN0_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN0_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN0_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN0_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN0_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN0_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN0_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN0_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN0_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN0_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN0_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN0_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN0_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN0_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN0_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN0_BIC_COE_SEL (3<<2) -#define m_WIN0_VSD_YRGB_GT4 (1<<4) -#define m_WIN0_VSD_YRGB_GT2 (1<<5) -#define m_WIN0_VSD_CBR_GT4 (1<<6) -#define m_WIN0_VSD_CBR_GT2 (1<<7) -#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN0_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN0_LINE_LOAD_MODE (1<<15) -#define m_WIN0_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN0_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN0_YRGB_HSD_MODE (3<<20) -#define m_WIN0_YRGB_VSU_MODE (1<<22) -#define m_WIN0_YRGB_VSD_MODE (1<<23) -#define m_WIN0_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN0_CBR_VER_SCL_MODE (3<<26) -#define m_WIN0_CBR_HSD_MODE (3<<28) -#define m_WIN0_CBR_VSU_MODE ((u32)1<<30) -#define m_WIN0_CBR_VSD_MODE ((u32)1<<31) - - -#define WIN0_COLOR_KEY (0x0038) -#define v_WIN0_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN0_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN0_COLOR_KEY (0x3fffffff<<0) -#define m_WIN0_COLOR_KEY_EN ((u32)1<<31) - -#define WIN0_VIR (0x003c) -#define v_WIN0_VIR_STRIDE(x) (((x)&0x3fff)<<0) -#define v_WIN0_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) -#define m_WIN0_VIR_STRIDE (0x3fff<<0) -#define m_WIN0_VIR_STRIDE_UV (0x3fff<<16) - -#define WIN0_YRGB_MST (0x0040) -#define WIN0_CBR_MST (0x0044) -#define WIN0_ACT_INFO (0x0048) -#define v_WIN0_ACT_WIDTH(x) (((x)&0x1fff)<<0) -#define v_WIN0_ACT_HEIGHT(x) (((x)&0x1fff)<<16) -#define m_WIN0_ACT_WIDTH (0x1fff<<0) -#define m_WIN0_ACT_HEIGHT (0x1fff<<16) - -#define WIN0_DSP_INFO (0x004c) -#define v_WIN0_DSP_WIDTH(x) (((x)&0xfff)<<0) -#define v_WIN0_DSP_HEIGHT(x) (((x)&0xfff)<<16) -#define m_WIN0_DSP_WIDTH (0xfff<<0) -#define m_WIN0_DSP_HEIGHT (0xfff<<16) - - -#define WIN0_DSP_ST (0x0050) -#define v_WIN0_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN0_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN0_DSP_XST (0x1fff<<0) -#define m_WIN0_DSP_YST (0x1fff<<16) - -#define WIN0_SCL_FACTOR_YRGB (0x0054) -#define v_WIN0_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN0_VS_FACTOR_YRGB ((u32)0xffff<<16) - - -#define WIN0_SCL_FACTOR_CBR (0x0058) -#define v_WIN0_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN0_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN0_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN0_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN0_SCL_OFFSET (0x005c) -#define v_WIN0_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN0_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN0_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN0_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN0_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN0_HS_OFFSET_CBR (0xff<<8) -#define m_WIN0_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN0_VS_OFFSET_CBR ((u32)0xff<<24) - - -#define WIN0_SRC_ALPHA_CTRL (0x0060) -#define v_WIN0_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN0_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN0_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN0_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN0_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN0_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN0_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_VALUE(x) (((x)&0xff)<<24) - - -#define m_WIN0_SRC_ALPHA_EN (1<<0) -#define m_WIN0_SRC_COLOR_M0 (1<<1) -#define m_WIN0_SRC_ALPHA_M0 (1<<2) -#define m_WIN0_SRC_BLEND_M0 (3<<3) -#define m_WIN0_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN0_SRC_FACTOR_M0 (7<<6) -#define m_WIN0_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN0_FADING_VALUE (0xff<<24) - -#define WIN0_DST_ALPHA_CTRL (0x0064) -#define v_WIN0_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN0_DST_FACTOR_M0 (7<<6) - - -#define WIN0_FADING_CTRL (0x0068) -#define v_WIN0_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN0_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN0_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN0_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN0_FADING_OFFSET_R (0xff<<0) -#define m_WIN0_FADING_OFFSET_G (0xff<<8) -#define m_WIN0_FADING_OFFSET_B (0xff<<16) -#define m_WIN0_FADING_EN (1<<24) - -//#define WIN0_RESERVED1 (0x006c) - -//win1 register -#define WIN1_CTRL0 (0x0070) -#define v_WIN1_EN(x) (((x)&1)<<0) -#define v_WIN1_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN1_FMT_10(x) (((x)&1)<<4) -#define v_WIN1_LB_MODE(x) (((x)&7)<<5) -//bit[7] reserved -#define v_WIN1_INTERLACE_READ_MODE(x) (((x)&1)<<8) -#define v_WIN1_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN1_CSC_MODE(x) (((x)&3)<<10) -#define v_WIN1_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN1_MID_SWAP(x) (((x)&1)<<14) -#define v_WIN1_UV_SWAP(x) (((x)&1)<<15) -#define v_WIN1_PPAS_ZERO_EN(x) (((x)&1)<<16) -#define v_WIN1_YRGB_DEFLICK(x) (((x)&1)<<18) -#define v_WIN1_CBR_DEFLICK(x) (((x)&1)<<19) -#define v_WIN1_YUV_CLIP(x) (((x)&1)<<20) - - -#define m_WIN1_EN (1<<0) -#define m_WIN1_DATA_FMT (7<<1) -#define m_WIN1_FMT_10 (1<<4) -#define m_WIN1_LB_MODE (3<<5) -//bit[7] reserved -#define m_WIN1_INTERLACE_READ_MODE (1<<8) -#define m_WIN1_NO_OUTSTANDING (1<<9) -#define m_WIN1_CSC_MODE (3<<10) -#define m_WIN1_RB_SWAP (1<<12) -#define m_WIN1_ALPHA_SWAP (1<<13) -#define m_WIN1_MID_SWAP (1<<14) -#define m_WIN1_UV_SWAP (1<<15) -#define m_WIN1_PPAS_ZERO_EN (1<<16) -#define m_WIN1_YRGB_DEFLICK (1<<18) -#define m_WIN1_CBR_DEFLICK (1<<19) -#define m_WIN1_YUV_CLIP (1<<20) - -#define WIN1_CTRL1 (0x0074) -#define v_WIN1_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) -#define v_WIN1_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) -#define v_WIN1_BIC_COE_SEL(x) (((x)&3)<<2) -#define v_WIN1_VSD_YRGB_GT4(x) (((x)&1)<<4) -#define v_WIN1_VSD_YRGB_GT2(x) (((x)&1)<<5) -#define v_WIN1_VSD_CBR_GT4(x) (((x)&1)<<6) -#define v_WIN1_VSD_CBR_GT2(x) (((x)&1)<<7) -#define v_WIN1_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) -#define v_WIN1_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) -#define v_WIN1_LINE_LOAD_MODE(x) (((x)&1)<<15) -#define v_WIN1_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) -#define v_WIN1_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) -#define v_WIN1_YRGB_HSD_MODE(x) (((x)&3)<<20) -#define v_WIN1_YRGB_VSU_MODE(x) (((x)&1)<<22) -#define v_WIN1_YRGB_VSD_MODE(x) (((x)&1)<<23) -#define v_WIN1_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) -#define v_WIN1_CBR_VER_SCL_MODE(x) (((x)&3)<<26) -#define v_WIN1_CBR_HSD_MODE(x) (((x)&3)<<28) -#define v_WIN1_CBR_VSU_MODE(x) (((x)&1)<<30) -#define v_WIN1_CBR_VSD_MODE(x) (((x)&1)<<31) - -#define m_WIN1_YRGB_AXI_GATHER_EN (1<<0) -#define m_WIN1_CBR_AXI_GATHER_EN (1<<1) -#define m_WIN1_BIC_COE_SEL (3<<2) -#define m_WIN1_VSD_YRGB_GT4 (1<<4) -#define m_WIN1_VSD_YRGB_GT2 (1<<5) -#define m_WIN1_VSD_CBR_GT4 (1<<6) -#define m_WIN1_VSD_CBR_GT2 (1<<7) -#define m_WIN1_YRGB_AXI_GATHER_NUM (0xf<<8) -#define m_WIN1_CBR_AXI_GATHER_NUM (7<<12) -#define m_WIN1_LINE_LOAD_MODE (1<<15) -#define m_WIN1_YRGB_HOR_SCL_MODE (3<<16) -#define m_WIN1_YRGB_VER_SCL_MODE (3<<18) -#define m_WIN1_YRGB_HSD_MODE (3<<20) -#define m_WIN1_YRGB_VSU_MODE (1<<22) -#define m_WIN1_YRGB_VSD_MODE (1<<23) -#define m_WIN1_CBR_HOR_SCL_MODE (3<<24) -#define m_WIN1_CBR_VER_SCL_MODE (3<<26) -#define m_WIN1_CBR_HSD_MODE (3<<28) -#define m_WIN1_CBR_VSU_MODE (1<<30) -#define m_WIN1_CBR_VSD_MODE ((u32)1<<31) - -#define WIN1_COLOR_KEY (0x0078) -#define v_WIN1_COLOR_KEY(x) (((x)&0x3fffffff)<<0) -#define v_WIN1_COLOR_KEY_EN(x) (((x)&1)<<31) -#define m_WIN1_COLOR_KEY (0x3fffffff<<0) -#define m_WIN1_COLOR_KEY_EN ((u32)1<<31) - -#define WIN1_VIR (0x007c) -#define v_WIN1_VIR_STRIDE(x) (((x)&0x3fff)<<0) -#define v_WIN1_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) -#define m_WIN1_VIR_STRIDE (0x3fff<<0) -#define m_WIN1_VIR_STRIDE_UV (0x3fff<<16) - - -#define WIN1_YRGB_MST (0x0080) -#define WIN1_CBR_MST (0x0084) -#define WIN1_ACT_INFO (0x0088) -#define v_WIN1_ACT_WIDTH(x) (((x)&0x1fff)<<0) -#define v_WIN1_ACT_HEIGHT(x) (((x)&0x1fff)<<16) -#define m_WIN1_ACT_WIDTH (0x1fff<<0) -#define m_WIN1_ACT_HEIGHT (0x1fff<<16) - -#define WIN1_DSP_INFO (0x008c) -#define v_WIN1_DSP_WIDTH(x) (((x)&0xfff)<<0) -#define v_WIN1_DSP_HEIGHT(x) (((x)&0xfff)<<16) -#define m_WIN1_DSP_WIDTH (0xfff<<0) -#define m_WIN1_DSP_HEIGHT (0xfff<<16) - - -#define WIN1_DSP_ST (0x0090) -#define v_WIN1_DSP_XST(x) (((x)&0x1fff)<<0) -#define v_WIN1_DSP_YST(x) (((x)&0x1fff)<<16) -#define m_WIN1_DSP_XST (0x1fff<<0) -#define m_WIN1_DSP_YST (0x1fff<<16) - -#define WIN1_SCL_FACTOR_YRGB (0x0094) -#define v_WIN1_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_YRGB (0xffff<<0) -#define m_WIN1_VS_FACTOR_YRGB ((u32)0xffff<<16) - - -#define WIN1_SCL_FACTOR_CBR (0x0098) -#define v_WIN1_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) -#define v_WIN1_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) -#define m_WIN1_HS_FACTOR_CBR (0xffff<<0) -#define m_WIN1_VS_FACTOR_CBR ((u32)0xffff<<16) - -#define WIN1_SCL_OFFSET (0x009c) -#define v_WIN1_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) -#define v_WIN1_HS_OFFSET_CBR(x) (((x)&0xff)<<8) -#define v_WIN1_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) -#define v_WIN1_VS_OFFSET_CBR(x) (((x)&0xff)<<24) - -#define m_WIN1_HS_OFFSET_YRGB (0xff<<0) -#define m_WIN1_HS_OFFSET_CBR (0xff<<8) -#define m_WIN1_VS_OFFSET_YRGB (0xff<<16) -#define m_WIN1_VS_OFFSET_CBR ((u32)0xff<<24) - - -#define WIN1_SRC_ALPHA_CTRL (0x00a0) -#define v_WIN1_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN1_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN1_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN1_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN1_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN1_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN1_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_VALUE(x) (((x)&0xff)<<24) - - -#define m_WIN1_SRC_ALPHA_EN (1<<0) -#define m_WIN1_SRC_COLOR_M0 (1<<1) -#define m_WIN1_SRC_ALPHA_M0 (1<<2) -#define m_WIN1_SRC_BLEND_M0 (3<<3) -#define m_WIN1_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN1_SRC_FACTOR_M0 (7<<6) -#define m_WIN1_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN1_FADING_VALUE (0xff<<24) - -#define WIN1_DST_ALPHA_CTRL (0x00a4) -#define v_WIN1_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN1_DST_FACTOR_M0 (7<<6) - - -#define WIN1_FADING_CTRL (0x00a8) -#define v_WIN1_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN1_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN1_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN1_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN1_FADING_OFFSET_R (0xff<<0) -#define m_WIN1_FADING_OFFSET_G (0xff<<8) -#define m_WIN1_FADING_OFFSET_B (0xff<<16) -#define m_WIN1_FADING_EN (1<<24) - - -//#define WIN1_RESERVED1 (0x00ac) - -//win2 register -#define WIN2_CTRL0 (0x00b0) -#define v_WIN2_EN(x) (((x)&1)<<0) -#define v_WIN2_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN2_MST0_EN(x) (((x)&1)<<4) -#define v_WIN2_MST1_EN(x) (((x)&1)<<5) -#define v_WIN2_MST2_EN(x) (((x)&1)<<6) -#define v_WIN2_MST3_EN(x) (((x)&1)<<7) -#define v_WIN2_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN2_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN2_CSC_MODE(x) (((x)&1)<<10) -//bit[11]reversed -#define v_WIN2_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN2_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN2_ENDIAN_MODE(x) (((x)&1)<<14) -//bit[15]reversed -#define v_WIN2_LUT_EN(x) (((x)&1)<<18) - -#define m_WIN2_EN (1<<0) -#define m_WIN2_DATA_FMT (7<<1) -#define m_WIN2_MST0_EN (1<<4) -#define m_WIN2_MST1_EN (1<<5) -#define m_WIN2_MST2_EN (1<<6) -#define m_WIN2_MST3_EN (1<<7) -#define m_WIN2_INTERLACE_READ (1<<8) -#define m_WIN2_NO_OUTSTANDING (1<<9) -#define m_WIN2_CSC_MODE (1<<10) -//bit[11]reversed -#define m_WIN2_RB_SWAP (1<<12) -#define m_WIN2_ALPHA_SWAP (1<<13) -#define m_WIN2_ENDIAN_MODE (1<<14) -//bit[15]reversed -#define m_WIN2_LUT_EN (1<<18) - -#define WIN2_CTRL1 (0x00b4) -#define v_WIN2_AXI_GATHER_EN(x) (((x)&1)<<0) -//bit[3:1]reserved -#define v_WIN2_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define m_WIN2_AXI_GATHER_EN (1<<0) -//bit[3:1]reserved -#define m_WIN2_AXI_GATHER_NUM (0xf<<4) - -#define WIN2_VIR0_1 (0x00b8) -#define v_WIN2_VIR_STRIDE0(x) (((x)&0x1fff)<<0) -#define v_WIN2_VIR_STRIDE1(x) (((x)&0x1fff)<<16) -#define m_WIN2_VIR_STRIDE0 (0x1fff<<0) -#define m_WIN2_VIR_STRIDE1 (0x1fff<<16) - -#define WIN2_VIR2_3 (0x00bc) -#define v_WIN2_VIR_STRIDE2(x) (((x)&0x1fff)<<0) -#define v_WIN2_VIR_STRIDE3(x) (((x)&0x1fff)<<16) -#define m_WIN2_VIR_STRIDE2 (0x1fff<<0) -#define m_WIN2_VIR_STRIDE3 (0x1fff<<16) - -#define WIN2_MST0 (0x00c0) -#define WIN2_DSP_INFO0 (0x00c4) -#define v_WIN2_DSP_WIDTH0(x) (((x)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT0(x) (((x)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH0 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT0 (0xfff<<16) - -#define WIN2_DSP_ST0 (0x00c8) -#define v_WIN2_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST0 (0x1fff<<0) -#define m_WIN2_DSP_YST0 (0x1fff<<16) - -#define WIN2_COLOR_KEY (0x00cc) -#define v_WIN2_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN2_KEY_EN(x) (((x)&1)<<24) -#define m_WIN2_COLOR_KEY (0xffffff<<0) -#define m_WIN2_KEY_EN ((u32)1<<24) - - -#define WIN2_MST1 (0x00d0) -#define WIN2_DSP_INFO1 (0x00d4) -#define v_WIN2_DSP_WIDTH1(x) (((x)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT1(x) (((x)&0xfff)<<16) - -#define m_WIN2_DSP_WIDTH1 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT1 (0xfff<<16) - -#define WIN2_DSP_ST1 (0x00d8) -#define v_WIN2_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST1(x) (((x)&0x1fff)<<16) - -#define m_WIN2_DSP_XST1 (0x1fff<<0) -#define m_WIN2_DSP_YST1 (0x1fff<<16) - -#define WIN2_SRC_ALPHA_CTRL (0x00dc) -#define v_WIN2_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN2_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN2_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN2_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN2_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN2_SRC_FACTOR_M0(x) (((x)&7)<<5) -#define v_WIN2_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_VALUE(x) (((x)&0xff)<<24) - - -#define m_WIN2_SRC_ALPHA_EN (1<<0) -#define m_WIN2_SRC_COLOR_M0 (1<<1) -#define m_WIN2_SRC_ALPHA_M0 (1<<2) -#define m_WIN2_SRC_BLEND_M0 (3<<3) -#define m_WIN2_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN2_SRC_FACTOR_M0 (7<<6) -#define m_WIN2_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN2_FADING_VALUE (0xff<<24) - -#define WIN2_MST2 (0x00e0) -#define WIN2_DSP_INFO2 (0x00e4) -#define v_WIN2_DSP_WIDTH2(x) (((x)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT2(x) (((x)&0xfff)<<16) - -#define m_WIN2_DSP_WIDTH2 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT2 (0xfff<<16) - - -#define WIN2_DSP_ST2 (0x00e8) -#define v_WIN2_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST2 (0x1fff<<0) -#define m_WIN2_DSP_YST2 (0x1fff<<16) - -#define WIN2_DST_ALPHA_CTRL (0x00ec) -#define v_WIN2_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN2_DST_FACTOR_M0 (7<<6) - -#define WIN2_MST3 (0x00f0) -#define WIN2_DSP_INFO3 (0x00f4) -#define v_WIN2_DSP_WIDTH3(x) (((x)&0xfff)<<0) -#define v_WIN2_DSP_HEIGHT3(x) (((x)&0xfff)<<16) -#define m_WIN2_DSP_WIDTH3 (0xfff<<0) -#define m_WIN2_DSP_HEIGHT3 (0xfff<<16) - -#define WIN2_DSP_ST3 (0x00f8) -#define v_WIN2_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN2_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN2_DSP_XST3 (0x1fff<<0) -#define m_WIN2_DSP_YST3 (0x1fff<<16) - -#define WIN2_FADING_CTRL (0x00fc) -#define v_WIN2_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN2_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN2_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN2_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN2_FADING_OFFSET_R (0xff<<0) -#define m_WIN2_FADING_OFFSET_G (0xff<<8) -#define m_WIN2_FADING_OFFSET_B (0xff<<16) -#define m_WIN2_FADING_EN (1<<24) - -//win3 register -#define WIN3_CTRL0 (0x0100) -#define v_WIN3_EN(x) (((x)&1)<<0) -#define v_WIN3_DATA_FMT(x) (((x)&7)<<1) -#define v_WIN3_MST0_EN(x) (((x)&1)<<4) -#define v_WIN3_MST1_EN(x) (((x)&1)<<5) -#define v_WIN3_MST2_EN(x) (((x)&1)<<6) -#define v_WIN3_MST3_EN(x) (((x)&1)<<7) -#define v_WIN3_INTERLACE_READ(x) (((x)&1)<<8) -#define v_WIN3_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_WIN3_CSC_MODE(x) (((x)&1)<<10) -//bit[11]reversed -#define v_WIN3_RB_SWAP(x) (((x)&1)<<12) -#define v_WIN3_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_WIN3_ENDIAN_MODE(x) (((x)&1)<<14) -//bit[15]reversed -#define v_WIN3_LUT_EN(x) (((x)&1)<<18) - -#define m_WIN3_EN (1<<0) -#define m_WIN3_DATA_FMT (7<<1) -#define m_WIN3_MST0_EN (1<<4) -#define m_WIN3_MST1_EN (1<<5) -#define m_WIN3_MST2_EN (1<<6) -#define m_WIN3_MST3_EN (1<<7) -#define m_WIN3_INTERLACE_READ (1<<8) -#define m_WIN3_NO_OUTSTANDING (1<<9) -#define m_WIN3_CSC_MODE (1<<10) -//bit[11]reversed -#define m_WIN3_RB_SWAP (1<<12) -#define m_WIN3_ALPHA_SWAP (1<<13) -#define m_WIN3_ENDIAN_MODE (1<<14) -//bit[15]reversed -#define m_WIN3_LUT_EN (1<<18) - - -#define WIN3_CTRL1 (0x0104) -#define v_WIN3_AXI_GATHER_EN(x) (((x)&1)<<0) -//bit[3:1]reserved -#define v_WIN3_AXI_GATHER_NUM(x) (((x)&0xf)<<4) -#define m_WIN3_AXI_GATHER_EN (1<<0) -//bit[3:1]reserved -#define m_WIN3_AXI_GATHER_NUM (0xf<<4) - -#define WIN3_VIR0_1 (0x0108) -#define v_WIN3_VIR_STRIDE0(x) (((x)&0x1fff)<<0) -#define v_WIN3_VIR_STRIDE1(x) (((x)&0x1fff)<<16) -#define m_WIN3_VIR_STRIDE0 (0x1fff<<0) -#define m_WIN3_VIR_STRIDE1 (0x1fff<<16) - -#define WIN3_VIR2_3 (0x010c) -#define v_WIN3_VIR_STRIDE2(x) (((x)&0x1fff)<<0) -#define v_WIN3_VIR_STRIDE3(x) (((x)&0x1fff)<<16) -#define m_WIN3_VIR_STRIDE2 (0x1fff<<0) -#define m_WIN3_VIR_STRIDE3 (0x1fff<<16) - - -#define WIN3_MST0 (0x0110) -#define WIN3_DSP_INFO0 (0x0114) -#define v_WIN3_DSP_WIDTH0(x) (((x)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT0(x) (((x)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH0 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT0 (0xfff<<16) - -#define WIN3_DSP_ST0 (0x0118) -#define v_WIN3_DSP_XST0(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST0(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST0 (0x1fff<<0) -#define m_WIN3_DSP_YST0 (0x1fff<<16) - -#define WIN3_COLOR_KEY (0x011c) -#define v_WIN3_COLOR_KEY(x) (((x)&0xffffff)<<0) -#define v_WIN3_KEY_EN(x) (((x)&1)<<24) -#define m_WIN3_COLOR_KEY (0xffffff<<0) -#define m_WIN3_KEY_EN ((u32)1<<24) - - - -#define WIN3_MST1 (0x0120) -#define WIN3_DSP_INFO1 (0x0124) -#define v_WIN3_DSP_WIDTH1(x) (((x)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT1(x) (((x)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH1 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT1 (0xfff<<16) - -#define WIN3_DSP_ST1 (0x0128) -#define v_WIN3_DSP_XST1(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST1(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST1 (0x1fff<<0) -#define m_WIN3_DSP_YST1 (0x1fff<<16) - -#define WIN3_SRC_ALPHA_CTRL (0x012c) -#define v_WIN3_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_WIN3_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_WIN3_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_WIN3_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_WIN3_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_WIN3_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_WIN3_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_WIN3_SRC_ALPHA_EN (1<<0) -#define m_WIN3_SRC_COLOR_M0 (1<<1) -#define m_WIN3_SRC_ALPHA_M0 (1<<2) -#define m_WIN3_SRC_BLEND_M0 (3<<3) -#define m_WIN3_SRC_ALPHA_CAL_M0 (1<<5) -#define m_WIN3_SRC_FACTOR_M0 (7<<6) -#define m_WIN3_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_WIN3_FADING_VALUE (0xff<<24) - -#define WIN3_MST2 (0x0130) -#define WIN3_DSP_INFO2 (0x0134) -#define v_WIN3_DSP_WIDTH2(x) (((x)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT2(x) (((x)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH2 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT2 (0xfff<<16) - -#define WIN3_DSP_ST2 (0x0138) -#define v_WIN3_DSP_XST2(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST2(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST2 (0x1fff<<0) -#define m_WIN3_DSP_YST2 (0x1fff<<16) - -#define WIN3_DST_ALPHA_CTRL (0x013c) -#define v_WIN3_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_WIN3_DST_FACTOR_M0 (7<<6) - - -#define WIN3_MST3 (0x0140) -#define WIN3_DSP_INFO3 (0x0144) -#define v_WIN3_DSP_WIDTH3(x) (((x)&0xfff)<<0) -#define v_WIN3_DSP_HEIGHT3(x) (((x)&0xfff)<<16) -#define m_WIN3_DSP_WIDTH3 (0xfff<<0) -#define m_WIN3_DSP_HEIGHT3 (0xfff<<16) - -#define WIN3_DSP_ST3 (0x0148) -#define v_WIN3_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_WIN3_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_WIN3_DSP_XST3 (0x1fff<<0) -#define m_WIN3_DSP_YST3 (0x1fff<<16) - -#define WIN3_FADING_CTRL (0x014c) -#define v_WIN3_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_WIN3_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_WIN3_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_WIN3_FADING_EN(x) (((x)&1)<<24) - -#define m_WIN3_FADING_OFFSET_R (0xff<<0) -#define m_WIN3_FADING_OFFSET_G (0xff<<8) -#define m_WIN3_FADING_OFFSET_B (0xff<<16) -#define m_WIN3_FADING_EN (1<<24) - - -//hwc register -#define HWC_CTRL0 (0x0150) -#define v_HWC_EN(x) (((x)&1)<<0) -#define v_HWC_DATA_FMT(x) (((x)&7)<<1) -#define v_HWC_MODE(x) (((x)&1)<<4) -#define v_HWC_SIZE(x) (((x)&3)<<5) -//bit[7] reserved -#define v_HWC_INTERLACE_READ(x) (((x)&1)<<8) -#define v_HWC_NO_OUTSTANDING(x) (((x)&1)<<9) -#define v_HWC_CSC_MODE(x) (((x)&1)<<10) -//bit[11]reserved -#define v_HWC_RB_SWAP(x) (((x)&1)<<12) -#define v_HWC_ALPHA_SWAP(x) (((x)&1)<<13) -#define v_HWC_ENDIAN_MODE(x) (((x)&1)<<14) -//bit[15]reserved -#define v_HWC_LUT_EN(x) (((x)&1)<<18) - -#define m_HWC_EN (1<<0) -#define m_HWC_DATA_FMT (7<<1) -#define m_HWC_MODE (1<<4) -#define m_HWC_SIZE (3<<5) -//bit[7] reserved -#define m_HWC_INTERLACE_READ (1<<8) -#define m_HWC_NO_OUTSTANDING (1<<9) -#define m_HWC_CSC_MODE (1<<10) -//bit[11]reserved -#define m_HWC_RB_SWAP (1<<12) -#define m_HWC_ALPHA_SWAP (1<<13) -#define m_HWC_ENDIAN_MODE (1<<14) -//bit[15]reserved -#define m_HWC_LUT_EN (1<<18) - - -#define HWC_CTRL1 (0x0154) -#define v_HWC_AXI_GATHER_EN(x) (((x)&1)<<0) -//bit[3:1]reserved -#define v_HWC_AXI_GATHER_NUM(x) (((x)&7)<<4) -#define m_HWC_AXI_GATHER_EN (1<<0) -//bit[3:1]reserved -#define m_HWC_AXI_GATHER_NUM (7<<4) - -#define HWC_MST (0x0158) -#define HWC_DSP_ST (0x015c) -#define v_HWC_DSP_XST3(x) (((x)&0x1fff)<<0) -#define v_HWC_DSP_YST3(x) (((x)&0x1fff)<<16) -#define m_HWC_DSP_XST3 (0x1fff<<0) -#define m_HWC_DSP_YST3 (0x1fff<<16) - - -#define HWC_SRC_ALPHA_CTRL (0x0160) -#define v_HWC_SRC_ALPHA_EN(x) (((x)&1)<<0) -#define v_HWC_SRC_COLOR_M0(x) (((x)&1)<<1) -#define v_HWC_SRC_ALPHA_M0(x) (((x)&1)<<2) -#define v_HWC_SRC_BLEND_M0(x) (((x)&3)<<3) -#define v_HWC_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) -#define v_HWC_SRC_FACTOR_M0(x) (((x)&7)<<6) -#define v_HWC_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) -#define v_HWC_FADING_VALUE(x) (((x)&0xff)<<24) - -#define m_HWC_SRC_ALPHA_EN (1<<0) -#define m_HWC_SRC_COLOR_M0 (1<<1) -#define m_HWC_SRC_ALPHA_M0 (1<<2) -#define m_HWC_SRC_BLEND_M0 (3<<3) -#define m_HWC_SRC_ALPHA_CAL_M0 (1<<5) -#define m_HWC_SRC_FACTOR_M0 (7<<6) -#define m_HWC_SRC_GLOBAL_ALPHA (0xff<<16) -#define m_HWC_FADING_VALUE (0xff<<24) - -#define HWC_DST_ALPHA_CTRL (0x0164) -#define v_HWC_DST_FACTOR_M0(x) (((x)&7)<<6) -#define m_HWC_DST_FACTOR_M0 (7<<6) - - -#define HWC_FADING_CTRL (0x0168) -#define v_HWC_FADING_OFFSET_R(x) (((x)&0xff)<<0) -#define v_HWC_FADING_OFFSET_G(x) (((x)&0xff)<<8) -#define v_HWC_FADING_OFFSET_B(x) (((x)&0xff)<<16) -#define v_HWC_FADING_EN(x) (((x)&1)<<24) - -#define m_HWC_FADING_OFFSET_R (0xff<<0) -#define m_HWC_FADING_OFFSET_G (0xff<<8) -#define m_HWC_FADING_OFFSET_B (0xff<<16) -#define m_HWC_FADING_EN (1<<24) - -//#define HWC_RESERVED1 (0x016c) - -//post process register -#define POST_DSP_HACT_INFO (0x0170) -#define v_DSP_HACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END_POST (0x1fff<<0) -#define m_DSP_HACT_ST_POST (0x1fff<<16) - -#define POST_DSP_VACT_INFO (0x0174) -#define v_DSP_VACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_POST (0x1fff<<0) -#define m_DSP_VACT_ST_POST (0x1fff<<16) - - -#define POST_SCL_FACTOR_YRGB (0x0178) -#define v_POST_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) -#define v_POST_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) -#define m_POST_HS_FACTOR_YRGB (0xffff<<0) -#define m_POST_VS_FACTOR_YRGB (0xffff<<16) - -//#define POST_SCL_FACTOR_CBR (0x017c)//reserved - -#define POST_SCL_CTRL (0x0180) -#define v_POST_HOR_SD_EN(x) (((x)&1)<<0) -#define v_POST_VER_SD_EN(x) (((x)&1)<<1) - -#define m_POST_HOR_SD_EN (0x1<<0) -#define m_POST_VER_SD_EN (0x1<<1) - - -#define POST_DSP_VACT_INFO_F1 (0x0184) -#define v_DSP_VACT_END_POST(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST_POST(x) (((x)&0x1fff)<<16) - -#define m_DSP_VACT_END_POST (0x1fff<<0) -#define m_DSP_VACT_ST_POST (0x1fff<<16) - -#define DSP_HTOTAL_HS_END (0x0188) -#define v_DSP_HS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_HTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_HS_PW (0x1fff<<0) -#define m_DSP_HTOTAL (0x1fff<<16) - -#define DSP_HACT_ST_END (0x018c) -#define v_DSP_HACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_HACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_HACT_END (0x1fff<<0) -#define m_DSP_HACT_ST (0x1fff<<16) - - -#define DSP_VTOTAL_VS_END (0x0190) -#define v_DSP_VS_PW(x) (((x)&0x1fff)<<0) -#define v_DSP_VTOTAL(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_PW (0x1fff<<0) -#define m_DSP_VTOTAL (0x1fff<<16) - - -#define DSP_VACT_ST_END (0x0194) -#define v_DSP_VACT_END(x) (((x)&0x1fff)<<0) -#define v_DSP_VACT_ST(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END (0x1fff<<0) -#define m_DSP_VACT_ST (0x1fff<<16) - - -#define DSP_VS_ST_END_F1 (0x0198) -#define v_DSP_VS_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VS_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VS_END_F1 (0x1fff<<0) -#define m_DSP_VS_ST_F1 (0x1fff<<16) - - -#define DSP_VACT_ST_END_F1 (0x019c) -#define v_DSP_VACT_END_F1(x) (((x)&0x1fff)<<0) -#define v_DSP_VAC_ST_F1(x) (((x)&0x1fff)<<16) -#define m_DSP_VACT_END_F1 (0x1fff<<0) -#define m_DSP_VAC_ST_F1 (0x1fff<<16) - - -//pwm register -#define PWM_CTRL (0x01a0) -#define v_PWM_EN(x) (((x)&1)<<0) -#define v_PWM_MODE(x) (((x)&3)<<1) - -#define v_DUTY_POL(x) (((x)&1)<<3) -#define v_INACTIVE_POL(x) (((x)&1)<<4) -#define v_OUTPUT_MODE(x) (((x)&1)<<5) -//bit[7:6]reserved -#define v_BL_EN(x) (((x)&1)<<8) -#define v_CLK_SEL(x) (((x)&1)<<9) -//bit[11:10]reserved -#define v_PRESCALE(x) (((x)&7)<<12) -//bit[15]reserved -#define v_SCALE(x) (((x)&0xff)<<16) -#define v_RPT(x) (((x)&0xff)<<24) - -#define m_PWM_EN (1<<0) -#define m_PWM_MODE (3<<1) - -#define m_DUTY_POL (1<<3) -#define m_INACTIVE_POL (1<<4) -#define m_OUTPUT_MODE (1<<5) -//bit[7:6]reserved -#define m_BL_EN (1<<8) -#define m_CLK_SEL (1<<9) -//bit[11:10]reserved -#define m_PRESCALE (7<<12) -//bit[15]reserved -#define m_SCALE (0xff<<16) -#define m_RPT ((u32)0xff<<24) - -#define PWM_PERIOD_HPR (0x01a4) -#define PWM_DUTY_LPR (0x01a8) -#define PWM_CNT (0x01ac) - -//BCSH register -#define BCSH_COLOR_BAR (0x01b0) -#define v_BCSH_EN(x) (((x)&1)<<0) -//bit[1]reserved -#define v_BCSH_COLOR_BAR_Y(x) (((x)&0x3ff)<<2) -#define v_BCSH_COLOR_BAR_U(x) (((x)&0x3ff)<<12) -#define v_BCSH_COLOR_BAR_V(x) (((x)&0x3ff)<<22) - -#define m_BCSH_EN (1<<0) -//bit[1]reserved -#define m_BCSH_COLOR_BAR_Y (0x3ff<<2) -#define m_BCSH_COLOR_BAR_U (0x3ff<<12) -#define m_BCSH_COLOR_BAR_V ((u32)0x3ff<<22) - -#define BCSH_BCS (0x01b4) -#define v_BCSH_BRIGHTNESS(x) (((x)&0xff)<<0) -#define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8) -//bit[19:17]reserved -#define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20) -#define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30) - -#define m_BCSH_BRIGHTNESS (0xff<<0) -#define m_BCSH_CONTRAST (0x1ff<<8) -//bit[19:17]reserved -#define m_BCSH_SAT_CON (0x3ff<<20) -#define m_BCSH_OUT_MODE ((u32)0x3<<30) - - -#define BCSH_H (0x01b8) -#define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0) -//bit[15:9]reserved -#define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16) - -#define m_BCSH_SIN_HUE (0x1ff<<0) -#define m_BCSH_COS_HUE (0x1ff<<16) - -//#define BCSH_RESERVED (0x01bc) - -//CABC register -#define CABC_CTRL0 (0x01c0) -#define v_CABC_EN(x) (((x)&1)<<0) -#define v_CABC_CALC_PIXEL_NUM(x) (((x)&0xfffffe)<<1) -#define v_CABC_STAGE_UP(x) (((x)&0xff)<<24) -#define m_CABC_EN (1<<0) -#define m_CABC_CALC_PIXEL_NUM (0xfffffe<<1) -#define m_CABC_STAGE_UP (0xff<<24) - - -#define CABC_CTRL1 (0x01c4) -#define v_CABC_TOTAL_NUM(x) (((x)&0xfffffe)<<1) -#define v_CABC_STAGE_DOWN(x) (((x)&0xff)<<24) -#define m_CABC_TOTAL_NUM (0xfffffe<<1) -#define m_CABC_STAGE_DOWN (0xff<<24) - -#define CABC_GAUSS_LINE0_0 (0x01c8) -#define v_CABC_T_LINE0_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE0_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE0_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE0_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE0_0 (0xff<<0) -#define m_CABC_T_LINE0_1 (0xff<<8) -#define m_CABC_T_LINE0_2 (0xff<<16) -#define m_CABC_T_LINE0_3 ((u32)0xff<<24) - -#define CABC_GAUSS_LINE0_1 (0x01cc) -#define v_CABC_T_LINE0_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE0_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE0_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE0_4 (0xff<<0) -#define m_CABC_T_LINE0_5 (0xff<<8) -#define m_CABC_T_LINE0_6 (0xff<<16) - - -#define CABC_GAUSS_LINE1_0 (0x01d0) -#define v_CABC_T_LINE1_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE1_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE1_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE1_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE1_0 (0xff<<0) -#define m_CABC_T_LINE1_1 (0xff<<8) -#define m_CABC_T_LINE1_2 (0xff<<16) -#define m_CABC_T_LINE1_3 ((u32)0xff<<24) - - -#define CABC_GAUSS_LINE1_1 (0x01d4) -#define v_CABC_T_LINE1_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE1_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE1_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE1_4 (0xff<<0) -#define m_CABC_T_LINE1_5 (0xff<<8) -#define m_CABC_T_LINE1_6 (0xff<<16) - - -#define CABC_GAUSS_LINE2_0 (0x01d8) -#define v_CABC_T_LINE2_0(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE2_1(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE2_2(x) (((x)&0xff)<<16) -#define v_CABC_T_LINE2_3(x) (((x)&0xff)<<24) -#define m_CABC_T_LINE2_0 (0xff<<0) -#define m_CABC_T_LINE2_1 (0xff<<8) -#define m_CABC_T_LINE2_2 (0xff<<16) -#define m_CABC_T_LINE2_3 ((u32)0xff<<24) - - -#define CABC_GAUSS_LINE2_1 (0x01dc) -#define v_CABC_T_LINE2_4(x) (((x)&0xff)<<0) -#define v_CABC_T_LINE2_5(x) (((x)&0xff)<<8) -#define v_CABC_T_LINE2_6(x) (((x)&0xff)<<16) -#define m_CABC_T_LINE2_4 (0xff<<0) -#define m_CABC_T_LINE2_5 (0xff<<8) -#define m_CABC_T_LINE2_6 (0xff<<16) - -//FRC register -#define FRC_LOWER01_0 (0x01e0) -#define v_FRC_LOWER01_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER01_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER01_FRM0 (0xffff<<0) -#define m_FRC_LOWER01_FRM1 ((u32)0xffff<<16) - -#define FRC_LOWER01_1 (0x01e4) -#define v_FRC_LOWER01_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER01_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER01_FRM2 (0xffff<<0) -#define m_FRC_LOWER01_FRM3 ((u32)0xffff<<16) - - -#define FRC_LOWER10_0 (0x01e8) -#define v_FRC_LOWER10_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER10_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER10_FRM0 (0xffff<<0) -#define m_FRC_LOWER10_FRM1 ((u32)0xffff<<16) - - -#define FRC_LOWER10_1 (0x01ec) -#define v_FRC_LOWER10_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER10_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER10_FRM2 (0xffff<<0) -#define m_FRC_LOWER10_FRM3 ((u32)0xffff<<16) - - -#define FRC_LOWER11_0 (0x01f0) -#define v_FRC_LOWER11_FRM0(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER11_FRM1(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER11_FRM0 (0xffff<<0) -#define m_FRC_LOWER11_FRM1 ((u32)0xffff<<16) - - -#define FRC_LOWER11_1 (0x01f4) -#define v_FRC_LOWER11_FRM2(x) (((x)&0xffff)<<0) -#define v_FRC_LOWER11_FRM3(x) (((x)&0xffff)<<16) -#define m_FRC_LOWER11_FRM2 (0xffff<<0) -#define m_FRC_LOWER11_FRM3 ((u32)0xffff<<16) -//#define FRC_RESERVED0 (0x01f8) -//#define FRC_RESERVED1 (0x01fc) -#define MMU_DTE_ADDR (0x0300) -#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0) -#define m_MMU_DTE_ADDR (0xffffffff<<0) -#define MMU_STATUS (0x0304) -#define v_PAGING_ENABLED(x) (((x)&1)<<0) -#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1) -#define v_STAIL_ACTIVE(x) (((x)&1)<<2) -#define v_MMU_IDLE(x) (((x)&1)<<3) -#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4) -#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5) -#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6) -#define m_PAGING_ENABLED (1<<0) -#define m_PAGE_FAULT_ACTIVE (1<<1) -#define m_STAIL_ACTIVE (1<<2) -#define m_MMU_IDLE (1<<3) -#define m_REPLAY_BUFFER_EMPTY (1<<4) -#define m_PAGE_FAULT_IS_WRITE (1<<5) -#define m_PAGE_FAULT_BUS_ID (0x1f<<6) -#define MMU_COMMAND (0x0308) -#define v_MMU_CMD(x) (((x)&0x3)<<0) -#define m_MMU_CMD (0x3<<0) -#define MMU_PAGE_FAULT_ADDR (0x030c) -#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0) -#define m_PAGE_FAULT_ADDR (0xffffffff<<0) -#define MMU_ZAP_ONE_LINE (0x0310) -#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0) -#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0) -#define MMU_INT_RAWSTAT (0x0314) -#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1) -#define m_PAGE_FAULT_RAWSTAT (1<<0) -#define m_READ_BUS_ERROR_RAWSTAT (1<<1) -#define MMU_INT_CLEAR (0x0318) -#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1) -#define m_PAGE_FAULT_CLEAR (1<<0) -#define m_READ_BUS_ERROR_CLEAR (1<<1) -#define MMU_INT_MASK (0x031c) -#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1) -#define m_PAGE_FAULT_MASK (1<<0) -#define m_READ_BUS_ERROR_MASK (1<<1) -#define MMU_INT_STATUS (0x0320) -#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0) -#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1) -#define m_PAGE_FAULT_STATUS (1<<0) -#define m_READ_BUS_ERROR_STATUS (1<<1) -#define MMU_AUTO_GATING (0x0324) -#define v_MMU_AUTO_GATING(x) (((x)&1)<<0) -#define m_MMU_AUTO_GATING (1<<0) - -#define WIN2_LUT_ADDR (0x0400) -#define WIN3_LUT_ADDR (0x0800) -#define HWC_LUT_ADDR (0x0c00) -#define GAMMA_LUT_ADDR (0x1000) -#define MCU_BYPASS_WPORT (0x2200) -#define MCU_BYPASS_RPORT (0x2300) - -#define PWM_MODE_ONE_SHOT (0x0) -#define PWM_MODE_CONTINUOUS (0x1) -#define PWM_MODE_CAPTURE (0x2) - -struct lcdc_device{ - int id; - struct rk_lcdc_driver driver; - struct device *dev; - struct rk_screen *screen; - - void __iomem *regs; - void *regsbak; //back up reg - u32 reg_phy_base; // physical basic address of lcdc register - u32 len; // physical map length of lcdc register - spinlock_t reg_lock; //one time only one process allowed to config the register - - int __iomem *dsp_lut_addr_base; - - int prop; /*used for primary or extended display device*/ - bool pre_init; - bool pwr18; /*if lcdc use 1.8v power supply*/ - bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed - u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc - - - unsigned int irq; - - struct clk *pd; //lcdc power domain - struct clk *hclk; //lcdc AHP clk - struct clk *dclk; //lcdc dclk - struct clk *aclk; //lcdc share memory frequency - u32 pixclock; - - u32 standby; //1:standby,0:wrok -}; - -static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - *_pv = v; - writel_relaxed(v,lcdc_dev->regs+offset); -} - -static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset) -{ - u32 v; - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - v = readl_relaxed(lcdc_dev->regs+offset); - *_pv = v; - return v; -} - -static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32 _v = readl_relaxed(lcdc_dev->regs+offset); - _v &= msk; - return (_v >> msk); -} - -static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) |= msk; - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) -{ - u32* _pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - writel_relaxed(*_pv,lcdc_dev->regs + offset); -} - -static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v) -{ - u32 *_pv = (u32*)lcdc_dev->regsbak; - _pv += (offset >> 2); - (*_pv) &= (~msk); - (*_pv) |= v; - writel_relaxed(*_pv,lcdc_dev->regs+offset); -} - -static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) -{ - writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); - dsb(); -} - -#define CUBIC_PRECISE 0 -#define CUBIC_SPLINE 1 -#define CUBIC_CATROM 2 -#define CUBIC_MITCHELL 3 - -#define CUBIC_MODE_SELETION CUBIC_PRECISE - -/*****************************************************************************************************/ -#define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 // 4.12 -#define SCALE_FACTOR_BILI_DN_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 // 0.16 - -#define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 //0.16 -#define SCALE_FACTOR_AVRG_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 // 0.16 -#define SCALE_FACTOR_BIC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT))) - -#define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 //NONE SCALE,vsd_bil -#define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 //VER SCALE DOWN BIL - -/*****************************************************************************************************/ - -//#define GET_SCALE_FACTOR_BILI(src, dst) ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1)) -//#define GET_SCALE_FACTOR_BIC(src, dst) ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1)) -//modified by hpz: -#define GET_SCALE_FACTOR_BILI_DN(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT-1)) / ((dst) - 1)) -#define GET_SCALE_FACTOR_BILI_UP(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT-1)) / ((dst) - 1)) -#define GET_SCALE_FACTOR_BIC(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT-1)) / ((dst) - 1)) - -/*****************************************************************/ -//NOTE: hardwareΪ½ÚÊ¡¿ªÏú, srcHÏȳéÐеõ½ (srcH+vScaleDnMult-1)/vScaleDnMult; È»ºóËõ·Å -#define GET_SCALE_DN_ACT_HEIGHT(srcH, vScaleDnMult) (((srcH)+(vScaleDnMult)-1)/(vScaleDnMult)) - -//#define VSKIP_MORE_PRECISE - -#ifdef VSKIP_MORE_PRECISE -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ - (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) -#else -#define MIN_SCALE_FACTOR_AFTER_VSKIP 1 -#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ - ((GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)) == (dstH))\ - ? (GET_SCALE_FACTOR_BILI_DN((srcH), (dstH))/(vScaleDnMult))\ - : GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) -#endif -/*****************************************************************/ - - -//ScaleFactor must >= dst/src, or pixels at end of line may be unused -//ScaleFactor must < dst/(src-1), or dst buffer may overflow -//avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))/((src) - 1)) //hxx_chg//src -//modified by hpz: -#define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT+1)))/(2*(src) - 1)) - -/*****************************************************************************************************/ -//Scale Coordinate Accumulate, x.16 -#define SCALE_COOR_ACC_FIXPOINT_SHIFT 16 -#define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT) -#define SCALE_COOR_ACC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT))) -#define SCALE_COOR_ACC_FIXPOINT_REVERT(x) ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_COOR_ACC_FIXPOINT(scaleFactor, factorFixpointShift) \ - ((scaleFactor) << (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorFixpointShift))) - - -/*****************************************************************************************************/ -//CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8 -#define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8 -#define SCALE_FILTER_FACTOR_FIXPOINT_ONE (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT) -#define SCALE_FILTER_FACTOR_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))) -#define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1) - -#define SCALE_GET_FILTER_FACTOR_FIXPOINT(coorAccumulate, coorAccFixpointShift) \ - (((coorAccumulate)>>((coorAccFixpointShift)-SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))&(SCALE_FILTER_FACTOR_FIXPOINT_ONE-1)) - -#define SCALE_OFFSET_FIXPOINT_SHIFT 8 -#define SCALE_OFFSET_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_OFFSET_FIXPOINT_SHIFT))) - -u32 getHardWareVSkipLines(u32 srcH, u32 dstH) -{ - u32 vScaleDnMult; - - if(srcH >= (u32)(4*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) - { - vScaleDnMult = 4; - } - else if(srcH >= (u32)(2*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) - { - vScaleDnMult = 2; - } - else - { - vScaleDnMult = 1; - } - - return vScaleDnMult; -} - - -enum -{ - LB_YUV_3840X5 = 0x0, - LB_YUV_2560X8 = 0x1, - LB_RGB_3840X2 = 0x2, - LB_RGB_2560X4 = 0x3, - LB_RGB_1920X5 = 0x4, - LB_RGB_1280X8 = 0x5 -}; - -enum -{ - SCALE_UP_BIL = 0x0, - SCALE_UP_BIC = 0x1 -}; - -enum -{ - SCALE_DOWN_BIL = 0x0, - SCALE_DOWN_AVG = 0x1 -}; - -//ALPHA BLENDING MODE -enum -{ // Fs Fd - AB_USER_DEFINE = 0x0, - AB_CLEAR = 0x1,// 0 0 - AB_SRC = 0x2,// 1 0 - AB_DST = 0x3,// 0 1 - AB_SRC_OVER = 0x4,// 1 1-As'' - AB_DST_OVER = 0x5,// 1-Ad'' 1 - AB_SRC_IN = 0x6, - AB_DST_IN = 0x7, - AB_SRC_OUT = 0x8, - AB_DST_OUT = 0x9, - AB_SRC_ATOP = 0xa, - AB_DST_ATOP = 0xb, - XOR = 0xc, - AB_SRC_OVER_GLOBAL = 0xd -}; //alpha_blending_mode -enum -{ - AA_STRAIGHT = 0x0, - AA_INVERSE = 0x1 -};//src_alpha_mode -enum -{ - AA_GLOBAL = 0x0, - AA_PER_PIX = 0x1, - AA_PER_PIX_GLOBAL = 0x2 -};//src_global_alpha_mode -enum -{ - AA_SAT = 0x0, - AA_NO_SAT = 0x1 -};//src_alpha_sel -enum -{ - AA_SRC_PRE_MUL = 0x0, - AA_SRC_NO_PRE_MUL = 0x1 -};//src_color_mode -enum -{ - AA_ZERO = 0x0, - AA_ONE = 0x1, - AA_SRC = 0x2, - AA_SRC_INVERSE = 0x3, - AA_SRC_GLOBAL = 0x4 -};//src_factor_mode && dst_factor_mode - -struct alpha_config{ - u8 src_alpha_mode; //win0_src_alpha_m0 - u8 src_global_alpha_val; //win0_src_global_alpha - u8 src_global_alpha_mode;//win0_src_blend_m0 - u8 src_alpha_sel; //win0_src_alpha_cal_m0 - u8 src_color_mode; //win0_src_color_m0 - u8 src_factor_mode; //win0_src_factor_m0 - u8 dst_factor_mode; //win0_dst_factor_m0 -}; -#endif +#ifndef RK3288_LCDC_H_ +#define RK3288_LCDC_H_ + +#include +#include +#include + + +/*******************register definition**********************/ + +#define REG_CFG_DONE (0x0000) +#define VERSION_INFO (0x0004) +#define m_RTL_VERSION (0xffff<<0) +#define m_FPGA_VERSION (0xffff<<16) +#define SYS_CTRL (0x0008) +#define v_DIRECT_PATH_EN(x) (((x)&1)<<0) +#define v_DIRECT_PATCH_SEL(x) (((x)&3)<<1) +#define v_DOUB_CHANNEL_EN(x) (((x)&1)<<3) +#define v_DOUB_CH_OVERLAP_NUM(x) (((x)&0xf)<<4) +#define v_EDPI_HALT_EN(x) (((x)&1)<<8) +#define v_EDPI_WMS_MODE(x) (((x)&1)<<9) +#define v_EDPI_WMS_FS(x) (((x)&1)<<10) +#define v_RGB_OUT_EN(x) (((x)&1)<<12) +#define v_HDMI_OUT_EN(x) (((x)&1)<<13) +#define v_EDP_OUT_EN(x) (((x)&1)<<14) +#define v_MIPI_OUT_EN(x) (((x)&1)<<15) +#define v_DMA_BURST_LENGTH(x) (((x)&3)<<18) +#define v_MMU_EN(x) (((x)&1)<<20) +#define v_DMA_STOP(x) (((x)&1)<<21) +#define v_STANDBY_EN(x) (((x)&1)<<22) +#define v_AUTO_GATING_EN(x) (((x)&1)<<23) + +#define m_DIRECT_PATH_EN (1<<0) +#define m_DIRECT_PATCH_SEL (3<<1) +#define m_DOUB_CHANNEL_EN (1<<3) +#define m_DOUB_CH_OVERLAP_NUM (0xf<<4) +#define m_EDPI_HALT_EN (1<<8) +#define m_EDPI_WMS_MODE (1<<9) +#define m_EDPI_WMS_FS (1<<10) +#define m_RGB_OUT_EN (1<<12) +#define m_HDMI_OUT_EN (1<<13) +#define m_EDP_OUT_EN (1<<14) +#define m_MIPI_OUT_EN (1<<15) +#define m_DMA_BURST_LENGTH (3<<18) +#define m_MMU_EN (1<<20) +#define m_DMA_STOP (1<<21) +#define m_STANDBY_EN (1<<22) +#define m_AUTO_GATING_EN (1<<23) +#define SYS_CTRL1 (0x000c) +#define v_NOC_HURRY_EN(x) (((x)&0x1 )<<0 ) +#define v_NOC_HURRY_VALUE(x) (((x)&0x3 )<<1 ) +#define v_NOC_HURRY_THRESHOLD(x) (((x)&0x3f)<<3 ) +#define v_NOC_QOS_EN(x) (((x)&0x1 )<<9 ) +#define v_NOC_WIN_QOS(x) (((x)&0x3 )<<10) +#define v_AXI_MAX_OUTSTANDING_EN(x) (((x)&0x1 )<<12) +#define v_AXI_OUTSTANDING_MAX_NUM(x) (((x)&0x1f)<<13) + +#define m_NOC_HURRY_EN (0x1 <<0 ) +#define m_NOC_HURRY_VALUE (0x3 <<1 ) +#define m_NOC_HURRY_THRESHOLD (0x3f<<3 ) +#define m_NOC_QOS_EN (0x1 <<9 ) +#define m_NOC_WIN_QOS (0x3 <<10) +#define m_AXI_MAX_OUTSTANDING_EN (0x1 <<12) +#define m_AXI_OUTSTANDING_MAX_NUM (0x1f<<13) + +#define DSP_CTRL0 (0x0010) +#define v_DSP_OUT_MODE(x) (((x)&0x0f)<<0) +#define v_DSP_HSYNC_POL(x) (((x)&1)<<4) +#define v_DSP_VSYNC_POL(x) (((x)&1)<<5) +#define v_DSP_DEN_POL(x) (((x)&1)<<6) +#define v_DSP_DCLK_POL(x) (((x)&1)<<7) +#define v_DSP_DCLK_DDR(x) (((x)&1)<<8) +#define v_DSP_DDR_PHASE(x) (((x)&1)<<9) +#define v_DSP_INTERLACE(x) (((x)&1)<<10) +#define v_DSP_FIELD_POL(x) (((x)&1)<<11) +#define v_DSP_BG_SWAP(x) (((x)&1)<<12) +#define v_DSP_RB_SWAP(x) (((x)&1)<<13) +#define v_DSP_RG_SWAP(x) (((x)&1)<<14) +#define v_DSP_DELTA_SWAP(x) (((x)&1)<<15) +#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<16) +#define v_DSP_OUT_ZERO(x) (((x)&1)<<17) +#define v_DSP_BLANK_EN(x) (((x)&1)<<18) +#define v_DSP_BLACK_EN(x) (((x)&1)<<19) +#define v_DSP_CCIR656_AVG(x) (((x)&1)<<20) +#define v_DSP_YUV_CLIP(x) (((x)&1)<<21) +#define v_DSP_X_MIR_EN(x) (((x)&1)<<22) +#define v_DSP_Y_MIR_EN(x) (((x)&1)<<23) +#define m_DSP_OUT_MODE (0x0f<<0) +#define m_DSP_HSYNC_POL (1<<4) +#define m_DSP_VSYNC_POL (1<<5) +#define m_DSP_DEN_POL (1<<6) +#define m_DSP_DCLK_POL (1<<7) +#define m_DSP_DCLK_DDR (1<<8) +#define m_DSP_DDR_PHASE (1<<9) +#define m_DSP_INTERLACE (1<<10) +#define m_DSP_FIELD_POL (1<<11) +#define m_DSP_BG_SWAP (1<<12) +#define m_DSP_RB_SWAP (1<<13) +#define m_DSP_RG_SWAP (1<<14) +#define m_DSP_DELTA_SWAP (1<<15) +#define m_DSP_DUMMY_SWAP (1<<16) +#define m_DSP_OUT_ZERO (1<<17) +#define m_DSP_BLANK_EN (1<<18) +#define m_DSP_BLACK_EN (1<<19) +#define m_DSP_CCIR656_AVG (1<<20) +#define m_DSP_YUV_CLIP (1<<21) +#define m_DSP_X_MIR_EN (1<<22) +#define m_DSP_Y_MIR_EN (1<<23) + +#define DSP_CTRL1 (0x0014) +#define v_DSP_LUT_EN(x) (((x)&1)<<0) +#define v_PRE_DITHER_DOWN_EN(x) (((x)&1)<<1) +#define v_DITHER_DOWN_EN(x) (((x)&1)<<2) +#define v_DITHER_DOWN_MODE(x) (((x)&1)<<3) +#define v_DITHER_DOWN_SEL(x) (((x)&1)<<4) +#define v_DITHER_UP_EN(x) (((x)&1)<<6) +#define v_DSP_LAYER0_SEL(x) (((x)&3)<<8) +#define v_DSP_LAYER1_SEL(x) (((x)&3)<<10) +#define v_DSP_LAYER2_SEL(x) (((x)&3)<<12) +#define v_DSP_LAYER3_SEL(x) (((x)&3)<<14) +#define m_DSP_LUT_EN (1<<0) +#define m_PRE_DITHER_DOWN_EN (1<<1) +#define m_DITHER_DOWN_EN (1<<2) +#define m_DITHER_DOWN_MODE (1<<3) +#define m_DITHER_DOWN_SEL (1<<4) +#define m_DITHER_UP_EN (1<<6) +#define m_DSP_LAYER0_SEL (3<<8) +#define m_DSP_LAYER1_SEL (3<<10) +#define m_DSP_LAYER2_SEL (3<<12) +#define m_DSP_LAYER3_SEL (3<<16) + +#define DSP_BG (0x0018) +#define v_DSP_BG_BLUE(x) (((x)&0x3ff)<<0) +#define v_DSP_BG_GREEN(x) (((x)&0x3ff)<<10) +#define v_DSP_BG_RED(x) (((x)&0x3ff)<<20) +#define m_DSP_BG_BLUE (0x3ff<<0) +#define m_DSP_BG_GREEN (0x3ff<<10) +#define m_DSP_BG_RED (0x3ff<<20) + +#define MCU_CTRL (0x001c) +#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0) +#define v_MCU_CS_PST(x) (((x)&0xf)<<6) +#define v_MCU_CS_PEND(x) (((x)&0x3f)<<10) +#define v_MCU_RW_PST(x) (((x)&0xf)<<16) +#define v_MCU_RW_PEND(x) (((x)&0x3f)<<20) +#define v_MCU_CLK_SEL(x) (((x)&1)<<26) +#define v_MCU_HOLD_MODE(x) (((x)&1)<<27) +#define v_MCU_FRAME_ST(x) (((x)&1)<<28) +#define v_MCU_RS(x) (((x)&1)<<29) +#define v_MCU_BYPASS(x) (((x)&1)<<30) +#define v_MCU_TYPE(x) (((x)&1)<<31) +#define m_MCU_PIX_TOTAL (0x3f<<0) +#define m_MCU_CS_PST (0xf<<6) +#define m_MCU_CS_PEND (0x3f<<10) +#define m_MCU_RW_PST (0xf<<16) +#define m_MCU_RW_PEND (0x3f<<20) +#define m_MCU_CLK_SEL (1<<26) +#define m_MCU_HOLD_MODE (1<<27) +#define m_MCU_FRAME_ST (1<<28) +#define m_MCU_RS (1<<29) +#define m_MCU_BYPASS (1<<30) +#define m_MCU_TYPE ((u32)1<<31) + +#define INTR_CTRL0 (0x0020) +#define v_DSP_HOLD_VALID_INTR_STS(x) (((x)&1)<<0) +#define v_FS_INTR_STS(x) (((x)&1)<<1) +#define v_LINE_FLAG_INTR_STS(x) (((x)&1)<<2) +#define v_BUS_ERROR_INTR_STS(x) (((x)&1)<<3) +#define v_DSP_HOLD_VALID_INTR_EN(x) (((x)&1)<<4) +#define v_FS_INTR_EN(x) (((x)&1)<<5) +#define v_LINE_FLAG_INTR_EN(x) (((x)&1)<<6) +#define v_BUS_ERROR_INTR_EN(x) (((x)&1)<<7) +#define v_DSP_HOLD_VALID_INTR_CLR(x) (((x)&1)<<8) +#define v_FS_INTR_CLR(x) (((x)&1)<<9) +#define v_LINE_FLAG_INTR_CLR(x) (((x)&1)<<10) +#define v_BUS_ERROR_INTR_CLR(x) (((x)&1)<<11) +#define v_DSP_LINE_FLAG_NUM(x) (((x)&0xfff)<<12) + +#define m_DSP_HOLD_VALID_INTR_STS (1<<0) +#define m_FS_INTR_STS (1<<1) +#define m_LINE_FLAG_INTR_STS (1<<2) +#define m_BUS_ERROR_INTR_STS (1<<3) +#define m_DSP_HOLD_VALID_INTR_EN (1<<4) +#define m_FS_INTR_EN (1<<5) +#define m_LINE_FLAG_INTR_EN (1<<6) +#define m_BUS_ERROR_INTR_EN (1<<7) +#define m_DSP_HOLD_VALID_INTR_CLR (1<<8) +#define m_FS_INTR_CLR (1<<9) +#define m_LINE_FLAG_INTR_CLR (1<<10) +#define m_BUS_ERROR_INTR_CLR (1<<11) +#define m_DSP_LINE_FLAG_NUM (0xfff<<12) + +#define INTR_CTRL1 (0x0024) +#define v_WIN0_EMPTY_INTR_STS(x) (((x)&1)<<0) +#define v_WIN1_EMPTY_INTR_STS(x) (((x)&1)<<1) +#define v_WIN2_EMPTY_INTR_STS(x) (((x)&1)<<2) +#define v_WIN3_EMPTY_INTR_STS(x) (((x)&1)<<3) +#define v_HWC_EMPTY_INTR_STS(x) (((x)&1)<<4) +#define v_POST_BUF_EMPTY_INTR_STS(x) (((x)&1)<<5) +#define v_PWM_GEN_INTR_STS(x) (((x)&1)<<6) +#define v_WIN0_EMPTY_INTR_EN(x) (((x)&1)<<8) +#define v_WIN1_EMPTY_INTR_EN(x) (((x)&1)<<9) +#define v_WIN2_EMPTY_INTR_EN(x) (((x)&1)<<10) +#define v_WIN3_EMPTY_INTR_EN(x) (((x)&1)<<11) +#define v_HWC_EMPTY_INTR_EN(x) (((x)&1)<<12) +#define v_POST_BUF_EMPTY_INTR_EN(x) (((x)&1)<<13) +#define v_PWM_GEN_INTR_EN(x) (((x)&1)<<14) +#define v_WIN0_EMPTY_INTR_CLR(x) (((x)&1)<<16) +#define v_WIN1_EMPTY_INTR_CLR(x) (((x)&1)<<17) +#define v_WIN2_EMPTY_INTR_CLR(x) (((x)&1)<<18) +#define v_WIN3_EMPTY_INTR_CLR(x) (((x)&1)<<19) +#define v_HWC_EMPTY_INTR_CLR(x) (((x)&1)<<20) +#define v_POST_BUF_EMPTY_INTR_CLR(x) (((x)&1)<<21) +#define v_PWM_GEN_INTR_CLR(x) (((x)&1)<<22) + +#define m_WIN0_EMPTY_INTR_STS (1<<0) +#define m_WIN1_EMPTY_INTR_STS (1<<1) +#define m_WIN2_EMPTY_INTR_STS (1<<2) +#define m_WIN3_EMPTY_INTR_STS (1<<3) +#define m_HWC_EMPTY_INTR_STS (1<<4) +#define m_POST_BUF_EMPTY_INTR_STS (1<<5) +#define m_PWM_GEN_INTR_STS (1<<6) +#define m_WIN0_EMPTY_INTR_EN (1<<8) +#define m_WIN1_EMPTY_INTR_EN (1<<9) +#define m_WIN2_EMPTY_INTR_EN (1<<10) +#define m_WIN3_EMPTY_INTR_EN (1<<11) +#define m_HWC_EMPTY_INTR_EN (1<<12) +#define m_POST_BUF_EMPTY_INTR_EN (1<<13) +#define m_PWM_GEN_INTR_EN (1<<14) +#define m_WIN0_EMPTY_INTR_CLR (1<<16) +#define m_WIN1_EMPTY_INTR_CLR (1<<17) +#define m_WIN2_EMPTY_INTR_CLR (1<<18) +#define m_WIN3_EMPTY_INTR_CLR (1<<19) +#define m_HWC_EMPTY_INTR_CLR (1<<20) +#define m_POST_BUF_EMPTY_INTR_CLR (1<<21) +#define m_PWM_GEN_INTR_CLR (1<<22) + +/*win0 register*/ +#define WIN0_CTRL0 (0x0030) +#define v_WIN0_EN(x) (((x)&1)<<0) +#define v_WIN0_DATA_FMT(x) (((x)&7)<<1) +#define v_WIN0_FMT_10(x) (((x)&1)<<4) +#define v_WIN0_LB_MODE(x) (((x)&7)<<5) +#define v_WIN0_INTERLACE_READ(x) (((x)&1)<<8) +#define v_WIN0_NO_OUTSTANDING(x) (((x)&1)<<9) +#define v_WIN0_CSC_MODE(x) (((x)&3)<<10) +#define v_WIN0_RB_SWAP(x) (((x)&1)<<12) +#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<13) +#define v_WIN0_MID_SWAP(x) (((x)&1)<<14) +#define v_WIN0_UV_SWAP(x) (((x)&1)<<15) +#define v_WIN0_PPAS_ZERO_EN(x) (((x)&1)<<16) +#define v_WIN0_YRGB_DEFLICK(x) (((x)&1)<<18) +#define v_WIN0_CBR_DEFLICK(x) (((x)&1)<<19) +#define v_WIN0_YUV_CLIP(x) (((x)&1)<<20) + +#define m_WIN0_EN (1<<0) +#define m_WIN0_DATA_FMT (7<<1) +#define m_WIN0_FMT_10 (1<<4) +#define m_WIN0_LB_MODE (3<<5) +#define m_WIN0_INTERLACE_READ (1<<8) +#define m_WIN0_NO_OUTSTANDING (1<<9) +#define m_WIN0_CSC_MODE (3<<10) +#define m_WIN0_RB_SWAP (1<<12) +#define m_WIN0_ALPHA_SWAP (1<<13) +#define m_WIN0_MID_SWAP (1<<14) +#define m_WIN0_UV_SWAP (1<<15) +#define m_WIN0_PPAS_ZERO_EN (1<<16) +#define m_WIN0_YRGB_DEFLICK (1<<18) +#define m_WIN0_CBR_DEFLICK (1<<19) +#define m_WIN0_YUV_CLIP (1<<20) + +#define WIN0_CTRL1 (0x0034) +#define v_WIN0_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) +#define v_WIN0_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) +#define v_WIN0_BIC_COE_SEL(x) (((x)&3)<<2) +#define v_WIN0_VSD_YRGB_GT4(x) (((x)&1)<<4) +#define v_WIN0_VSD_YRGB_GT2(x) (((x)&1)<<5) +#define v_WIN0_VSD_CBR_GT4(x) (((x)&1)<<6) +#define v_WIN0_VSD_CBR_GT2(x) (((x)&1)<<7) +#define v_WIN0_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) +#define v_WIN0_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) +#define v_WIN0_LINE_LOAD_MODE(x) (((x)&1)<<15) +#define v_WIN0_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) +#define v_WIN0_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) +#define v_WIN0_YRGB_HSD_MODE(x) (((x)&3)<<20) +#define v_WIN0_YRGB_VSU_MODE(x) (((x)&1)<<22) +#define v_WIN0_YRGB_VSD_MODE(x) (((x)&1)<<23) +#define v_WIN0_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) +#define v_WIN0_CBR_VER_SCL_MODE(x) (((x)&3)<<26) +#define v_WIN0_CBR_HSD_MODE(x) (((x)&3)<<28) +#define v_WIN0_CBR_VSU_MODE(x) (((x)&1)<<30) +#define v_WIN0_CBR_VSD_MODE(x) (((x)&1)<<31) + +#define m_WIN0_YRGB_AXI_GATHER_EN (1<<0) +#define m_WIN0_CBR_AXI_GATHER_EN (1<<1) +#define m_WIN0_BIC_COE_SEL (3<<2) +#define m_WIN0_VSD_YRGB_GT4 (1<<4) +#define m_WIN0_VSD_YRGB_GT2 (1<<5) +#define m_WIN0_VSD_CBR_GT4 (1<<6) +#define m_WIN0_VSD_CBR_GT2 (1<<7) +#define m_WIN0_YRGB_AXI_GATHER_NUM (0xf<<8) +#define m_WIN0_CBR_AXI_GATHER_NUM (7<<12) +#define m_WIN0_LINE_LOAD_MODE (1<<15) +#define m_WIN0_YRGB_HOR_SCL_MODE (3<<16) +#define m_WIN0_YRGB_VER_SCL_MODE (3<<18) +#define m_WIN0_YRGB_HSD_MODE (3<<20) +#define m_WIN0_YRGB_VSU_MODE (1<<22) +#define m_WIN0_YRGB_VSD_MODE (1<<23) +#define m_WIN0_CBR_HOR_SCL_MODE (3<<24) +#define m_WIN0_CBR_VER_SCL_MODE (3<<26) +#define m_WIN0_CBR_HSD_MODE (3<<28) +#define m_WIN0_CBR_VSU_MODE ((u32)1<<30) +#define m_WIN0_CBR_VSD_MODE ((u32)1<<31) + +#define WIN0_COLOR_KEY (0x0038) +#define v_WIN0_COLOR_KEY(x) (((x)&0x3fffffff)<<0) +#define v_WIN0_COLOR_KEY_EN(x) (((x)&1)<<31) +#define m_WIN0_COLOR_KEY (0x3fffffff<<0) +#define m_WIN0_COLOR_KEY_EN ((u32)1<<31) + +#define WIN0_VIR (0x003c) +#define v_WIN0_VIR_STRIDE(x) (((x)&0x3fff)<<0) +#define v_WIN0_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) +#define m_WIN0_VIR_STRIDE (0x3fff<<0) +#define m_WIN0_VIR_STRIDE_UV (0x3fff<<16) + +#define WIN0_YRGB_MST (0x0040) +#define WIN0_CBR_MST (0x0044) +#define WIN0_ACT_INFO (0x0048) +#define v_WIN0_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) +#define v_WIN0_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) +#define m_WIN0_ACT_WIDTH (0x1fff<<0) +#define m_WIN0_ACT_HEIGHT (0x1fff<<16) + +#define WIN0_DSP_INFO (0x004c) +#define v_WIN0_DSP_WIDTH(x) (((x-1)&0xfff)<<0) +#define v_WIN0_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) +#define m_WIN0_DSP_WIDTH (0xfff<<0) +#define m_WIN0_DSP_HEIGHT (0xfff<<16) + +#define WIN0_DSP_ST (0x0050) +#define v_WIN0_DSP_XST(x) (((x)&0x1fff)<<0) +#define v_WIN0_DSP_YST(x) (((x)&0x1fff)<<16) +#define m_WIN0_DSP_XST (0x1fff<<0) +#define m_WIN0_DSP_YST (0x1fff<<16) + +#define WIN0_SCL_FACTOR_YRGB (0x0054) +#define v_WIN0_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) +#define v_WIN0_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) +#define m_WIN0_HS_FACTOR_YRGB (0xffff<<0) +#define m_WIN0_VS_FACTOR_YRGB ((u32)0xffff<<16) + +#define WIN0_SCL_FACTOR_CBR (0x0058) +#define v_WIN0_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) +#define v_WIN0_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) +#define m_WIN0_HS_FACTOR_CBR (0xffff<<0) +#define m_WIN0_VS_FACTOR_CBR ((u32)0xffff<<16) + +#define WIN0_SCL_OFFSET (0x005c) +#define v_WIN0_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) +#define v_WIN0_HS_OFFSET_CBR(x) (((x)&0xff)<<8) +#define v_WIN0_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) +#define v_WIN0_VS_OFFSET_CBR(x) (((x)&0xff)<<24) + +#define m_WIN0_HS_OFFSET_YRGB (0xff<<0) +#define m_WIN0_HS_OFFSET_CBR (0xff<<8) +#define m_WIN0_VS_OFFSET_YRGB (0xff<<16) +#define m_WIN0_VS_OFFSET_CBR ((u32)0xff<<24) + +#define WIN0_SRC_ALPHA_CTRL (0x0060) +#define v_WIN0_SRC_ALPHA_EN(x) (((x)&1)<<0) +#define v_WIN0_SRC_COLOR_M0(x) (((x)&1)<<1) +#define v_WIN0_SRC_ALPHA_M0(x) (((x)&1)<<2) +#define v_WIN0_SRC_BLEND_M0(x) (((x)&3)<<3) +#define v_WIN0_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) +#define v_WIN0_SRC_FACTOR_M0(x) (((x)&7)<<6) +#define v_WIN0_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) +#define v_WIN0_FADING_VALUE(x) (((x)&0xff)<<24) + +#define m_WIN0_SRC_ALPHA_EN (1<<0) +#define m_WIN0_SRC_COLOR_M0 (1<<1) +#define m_WIN0_SRC_ALPHA_M0 (1<<2) +#define m_WIN0_SRC_BLEND_M0 (3<<3) +#define m_WIN0_SRC_ALPHA_CAL_M0 (1<<5) +#define m_WIN0_SRC_FACTOR_M0 (7<<6) +#define m_WIN0_SRC_GLOBAL_ALPHA (0xff<<16) +#define m_WIN0_FADING_VALUE (0xff<<24) + +#define WIN0_DST_ALPHA_CTRL (0x0064) +#define v_WIN0_DST_FACTOR_M0(x) (((x)&7)<<6) +#define m_WIN0_DST_FACTOR_M0 (7<<6) + +#define WIN0_FADING_CTRL (0x0068) +#define v_WIN0_FADING_OFFSET_R(x) (((x)&0xff)<<0) +#define v_WIN0_FADING_OFFSET_G(x) (((x)&0xff)<<8) +#define v_WIN0_FADING_OFFSET_B(x) (((x)&0xff)<<16) +#define v_WIN0_FADING_EN(x) (((x)&1)<<24) + +#define m_WIN0_FADING_OFFSET_R (0xff<<0) +#define m_WIN0_FADING_OFFSET_G (0xff<<8) +#define m_WIN0_FADING_OFFSET_B (0xff<<16) +#define m_WIN0_FADING_EN (1<<24) + +/*win1 register*/ +#define WIN1_CTRL0 (0x0070) +#define v_WIN1_EN(x) (((x)&1)<<0) +#define v_WIN1_DATA_FMT(x) (((x)&7)<<1) +#define v_WIN1_FMT_10(x) (((x)&1)<<4) +#define v_WIN1_LB_MODE(x) (((x)&7)<<5) +#define v_WIN1_INTERLACE_READ_MODE(x) (((x)&1)<<8) +#define v_WIN1_NO_OUTSTANDING(x) (((x)&1)<<9) +#define v_WIN1_CSC_MODE(x) (((x)&3)<<10) +#define v_WIN1_RB_SWAP(x) (((x)&1)<<12) +#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<13) +#define v_WIN1_MID_SWAP(x) (((x)&1)<<14) +#define v_WIN1_UV_SWAP(x) (((x)&1)<<15) +#define v_WIN1_PPAS_ZERO_EN(x) (((x)&1)<<16) +#define v_WIN1_YRGB_DEFLICK(x) (((x)&1)<<18) +#define v_WIN1_CBR_DEFLICK(x) (((x)&1)<<19) +#define v_WIN1_YUV_CLIP(x) (((x)&1)<<20) + +#define m_WIN1_EN (1<<0) +#define m_WIN1_DATA_FMT (7<<1) +#define m_WIN1_FMT_10 (1<<4) +#define m_WIN1_LB_MODE (3<<5) +#define m_WIN1_INTERLACE_READ_MODE (1<<8) +#define m_WIN1_NO_OUTSTANDING (1<<9) +#define m_WIN1_CSC_MODE (3<<10) +#define m_WIN1_RB_SWAP (1<<12) +#define m_WIN1_ALPHA_SWAP (1<<13) +#define m_WIN1_MID_SWAP (1<<14) +#define m_WIN1_UV_SWAP (1<<15) +#define m_WIN1_PPAS_ZERO_EN (1<<16) +#define m_WIN1_YRGB_DEFLICK (1<<18) +#define m_WIN1_CBR_DEFLICK (1<<19) +#define m_WIN1_YUV_CLIP (1<<20) + +#define WIN1_CTRL1 (0x0074) +#define v_WIN1_YRGB_AXI_GATHER_EN(x) (((x)&1)<<0) +#define v_WIN1_CBR_AXI_GATHER_EN(x) (((x)&1)<<1) +#define v_WIN1_BIC_COE_SEL(x) (((x)&3)<<2) +#define v_WIN1_VSD_YRGB_GT4(x) (((x)&1)<<4) +#define v_WIN1_VSD_YRGB_GT2(x) (((x)&1)<<5) +#define v_WIN1_VSD_CBR_GT4(x) (((x)&1)<<6) +#define v_WIN1_VSD_CBR_GT2(x) (((x)&1)<<7) +#define v_WIN1_YRGB_AXI_GATHER_NUM(x) (((x)&0xf)<<8) +#define v_WIN1_CBR_AXI_GATHER_NUM(x) (((x)&7)<<12) +#define v_WIN1_LINE_LOAD_MODE(x) (((x)&1)<<15) +#define v_WIN1_YRGB_HOR_SCL_MODE(x) (((x)&3)<<16) +#define v_WIN1_YRGB_VER_SCL_MODE(x) (((x)&3)<<18) +#define v_WIN1_YRGB_HSD_MODE(x) (((x)&3)<<20) +#define v_WIN1_YRGB_VSU_MODE(x) (((x)&1)<<22) +#define v_WIN1_YRGB_VSD_MODE(x) (((x)&1)<<23) +#define v_WIN1_CBR_HOR_SCL_MODE(x) (((x)&3)<<24) +#define v_WIN1_CBR_VER_SCL_MODE(x) (((x)&3)<<26) +#define v_WIN1_CBR_HSD_MODE(x) (((x)&3)<<28) +#define v_WIN1_CBR_VSU_MODE(x) (((x)&1)<<30) +#define v_WIN1_CBR_VSD_MODE(x) (((x)&1)<<31) + +#define m_WIN1_YRGB_AXI_GATHER_EN (1<<0) +#define m_WIN1_CBR_AXI_GATHER_EN (1<<1) +#define m_WIN1_BIC_COE_SEL (3<<2) +#define m_WIN1_VSD_YRGB_GT4 (1<<4) +#define m_WIN1_VSD_YRGB_GT2 (1<<5) +#define m_WIN1_VSD_CBR_GT4 (1<<6) +#define m_WIN1_VSD_CBR_GT2 (1<<7) +#define m_WIN1_YRGB_AXI_GATHER_NUM (0xf<<8) +#define m_WIN1_CBR_AXI_GATHER_NUM (7<<12) +#define m_WIN1_LINE_LOAD_MODE (1<<15) +#define m_WIN1_YRGB_HOR_SCL_MODE (3<<16) +#define m_WIN1_YRGB_VER_SCL_MODE (3<<18) +#define m_WIN1_YRGB_HSD_MODE (3<<20) +#define m_WIN1_YRGB_VSU_MODE (1<<22) +#define m_WIN1_YRGB_VSD_MODE (1<<23) +#define m_WIN1_CBR_HOR_SCL_MODE (3<<24) +#define m_WIN1_CBR_VER_SCL_MODE (3<<26) +#define m_WIN1_CBR_HSD_MODE (3<<28) +#define m_WIN1_CBR_VSU_MODE (1<<30) +#define m_WIN1_CBR_VSD_MODE ((u32)1<<31) + +#define WIN1_COLOR_KEY (0x0078) +#define v_WIN1_COLOR_KEY(x) (((x)&0x3fffffff)<<0) +#define v_WIN1_COLOR_KEY_EN(x) (((x)&1)<<31) +#define m_WIN1_COLOR_KEY (0x3fffffff<<0) +#define m_WIN1_COLOR_KEY_EN ((u32)1<<31) + +#define WIN1_VIR (0x007c) +#define v_WIN1_VIR_STRIDE(x) (((x)&0x3fff)<<0) +#define v_WIN1_VIR_STRIDE_UV(x) (((x)&0x3fff)<<16) +#define m_WIN1_VIR_STRIDE (0x3fff<<0) +#define m_WIN1_VIR_STRIDE_UV (0x3fff<<16) + +#define WIN1_YRGB_MST (0x0080) +#define WIN1_CBR_MST (0x0084) +#define WIN1_ACT_INFO (0x0088) +#define v_WIN1_ACT_WIDTH(x) (((x-1)&0x1fff)<<0) +#define v_WIN1_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16) +#define m_WIN1_ACT_WIDTH (0x1fff<<0) +#define m_WIN1_ACT_HEIGHT (0x1fff<<16) + +#define WIN1_DSP_INFO (0x008c) +#define v_WIN1_DSP_WIDTH(x) (((x-1)&0xfff)<<0) +#define v_WIN1_DSP_HEIGHT(x) (((x-1)&0xfff)<<16) +#define m_WIN1_DSP_WIDTH (0xfff<<0) +#define m_WIN1_DSP_HEIGHT (0xfff<<16) + +#define WIN1_DSP_ST (0x0090) +#define v_WIN1_DSP_XST(x) (((x)&0x1fff)<<0) +#define v_WIN1_DSP_YST(x) (((x)&0x1fff)<<16) +#define m_WIN1_DSP_XST (0x1fff<<0) +#define m_WIN1_DSP_YST (0x1fff<<16) + +#define WIN1_SCL_FACTOR_YRGB (0x0094) +#define v_WIN1_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) +#define v_WIN1_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) +#define m_WIN1_HS_FACTOR_YRGB (0xffff<<0) +#define m_WIN1_VS_FACTOR_YRGB ((u32)0xffff<<16) + +#define WIN1_SCL_FACTOR_CBR (0x0098) +#define v_WIN1_HS_FACTOR_CBR(x) (((x)&0xffff)<<0) +#define v_WIN1_VS_FACTOR_CBR(x) (((x)&0xffff)<<16) +#define m_WIN1_HS_FACTOR_CBR (0xffff<<0) +#define m_WIN1_VS_FACTOR_CBR ((u32)0xffff<<16) + +#define WIN1_SCL_OFFSET (0x009c) +#define v_WIN1_HS_OFFSET_YRGB(x) (((x)&0xff)<<0) +#define v_WIN1_HS_OFFSET_CBR(x) (((x)&0xff)<<8) +#define v_WIN1_VS_OFFSET_YRGB(x) (((x)&0xff)<<16) +#define v_WIN1_VS_OFFSET_CBR(x) (((x)&0xff)<<24) + +#define m_WIN1_HS_OFFSET_YRGB (0xff<<0) +#define m_WIN1_HS_OFFSET_CBR (0xff<<8) +#define m_WIN1_VS_OFFSET_YRGB (0xff<<16) +#define m_WIN1_VS_OFFSET_CBR ((u32)0xff<<24) + +#define WIN1_SRC_ALPHA_CTRL (0x00a0) +#define v_WIN1_SRC_ALPHA_EN(x) (((x)&1)<<0) +#define v_WIN1_SRC_COLOR_M0(x) (((x)&1)<<1) +#define v_WIN1_SRC_ALPHA_M0(x) (((x)&1)<<2) +#define v_WIN1_SRC_BLEND_M0(x) (((x)&3)<<3) +#define v_WIN1_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) +#define v_WIN1_SRC_FACTOR_M0(x) (((x)&7)<<6) +#define v_WIN1_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) +#define v_WIN1_FADING_VALUE(x) (((x)&0xff)<<24) + +#define m_WIN1_SRC_ALPHA_EN (1<<0) +#define m_WIN1_SRC_COLOR_M0 (1<<1) +#define m_WIN1_SRC_ALPHA_M0 (1<<2) +#define m_WIN1_SRC_BLEND_M0 (3<<3) +#define m_WIN1_SRC_ALPHA_CAL_M0 (1<<5) +#define m_WIN1_SRC_FACTOR_M0 (7<<6) +#define m_WIN1_SRC_GLOBAL_ALPHA (0xff<<16) +#define m_WIN1_FADING_VALUE (0xff<<24) + +#define WIN1_DST_ALPHA_CTRL (0x00a4) +#define v_WIN1_DST_FACTOR_M0(x) (((x)&7)<<6) +#define m_WIN1_DST_FACTOR_M0 (7<<6) + +#define WIN1_FADING_CTRL (0x00a8) +#define v_WIN1_FADING_OFFSET_R(x) (((x)&0xff)<<0) +#define v_WIN1_FADING_OFFSET_G(x) (((x)&0xff)<<8) +#define v_WIN1_FADING_OFFSET_B(x) (((x)&0xff)<<16) +#define v_WIN1_FADING_EN(x) (((x)&1)<<24) + +#define m_WIN1_FADING_OFFSET_R (0xff<<0) +#define m_WIN1_FADING_OFFSET_G (0xff<<8) +#define m_WIN1_FADING_OFFSET_B (0xff<<16) +#define m_WIN1_FADING_EN (1<<24) + +/*win2 register*/ +#define WIN2_CTRL0 (0x00b0) +#define v_WIN2_EN(x) (((x)&1)<<0) +#define v_WIN2_DATA_FMT(x) (((x)&7)<<1) +#define v_WIN2_MST0_EN(x) (((x)&1)<<4) +#define v_WIN2_MST1_EN(x) (((x)&1)<<5) +#define v_WIN2_MST2_EN(x) (((x)&1)<<6) +#define v_WIN2_MST3_EN(x) (((x)&1)<<7) +#define v_WIN2_INTERLACE_READ(x) (((x)&1)<<8) +#define v_WIN2_NO_OUTSTANDING(x) (((x)&1)<<9) +#define v_WIN2_CSC_MODE(x) (((x)&1)<<10) +#define v_WIN2_RB_SWAP(x) (((x)&1)<<12) +#define v_WIN2_ALPHA_SWAP(x) (((x)&1)<<13) +#define v_WIN2_ENDIAN_MODE(x) (((x)&1)<<14) +#define v_WIN2_LUT_EN(x) (((x)&1)<<18) + +#define m_WIN2_EN (1<<0) +#define m_WIN2_DATA_FMT (7<<1) +#define m_WIN2_MST0_EN (1<<4) +#define m_WIN2_MST1_EN (1<<5) +#define m_WIN2_MST2_EN (1<<6) +#define m_WIN2_MST3_EN (1<<7) +#define m_WIN2_INTERLACE_READ (1<<8) +#define m_WIN2_NO_OUTSTANDING (1<<9) +#define m_WIN2_CSC_MODE (1<<10) +#define m_WIN2_RB_SWAP (1<<12) +#define m_WIN2_ALPHA_SWAP (1<<13) +#define m_WIN2_ENDIAN_MODE (1<<14) +#define m_WIN2_LUT_EN (1<<18) + +#define WIN2_CTRL1 (0x00b4) +#define v_WIN2_AXI_GATHER_EN(x) (((x)&1)<<0) +#define v_WIN2_AXI_GATHER_NUM(x) (((x)&0xf)<<4) +#define m_WIN2_AXI_GATHER_EN (1<<0) +#define m_WIN2_AXI_GATHER_NUM (0xf<<4) + +#define WIN2_VIR0_1 (0x00b8) +#define v_WIN2_VIR_STRIDE0(x) (((x)&0x1fff)<<0) +#define v_WIN2_VIR_STRIDE1(x) (((x)&0x1fff)<<16) +#define m_WIN2_VIR_STRIDE0 (0x1fff<<0) +#define m_WIN2_VIR_STRIDE1 (0x1fff<<16) + +#define WIN2_VIR2_3 (0x00bc) +#define v_WIN2_VIR_STRIDE2(x) (((x)&0x1fff)<<0) +#define v_WIN2_VIR_STRIDE3(x) (((x)&0x1fff)<<16) +#define m_WIN2_VIR_STRIDE2 (0x1fff<<0) +#define m_WIN2_VIR_STRIDE3 (0x1fff<<16) + +#define WIN2_MST0 (0x00c0) +#define WIN2_DSP_INFO0 (0x00c4) +#define v_WIN2_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) +#define v_WIN2_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) +#define m_WIN2_DSP_WIDTH0 (0xfff<<0) +#define m_WIN2_DSP_HEIGHT0 (0xfff<<16) + +#define WIN2_DSP_ST0 (0x00c8) +#define v_WIN2_DSP_XST0(x) (((x)&0x1fff)<<0) +#define v_WIN2_DSP_YST0(x) (((x)&0x1fff)<<16) +#define m_WIN2_DSP_XST0 (0x1fff<<0) +#define m_WIN2_DSP_YST0 (0x1fff<<16) + +#define WIN2_COLOR_KEY (0x00cc) +#define v_WIN2_COLOR_KEY(x) (((x)&0xffffff)<<0) +#define v_WIN2_KEY_EN(x) (((x)&1)<<24) +#define m_WIN2_COLOR_KEY (0xffffff<<0) +#define m_WIN2_KEY_EN ((u32)1<<24) + + +#define WIN2_MST1 (0x00d0) +#define WIN2_DSP_INFO1 (0x00d4) +#define v_WIN2_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) +#define v_WIN2_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) + +#define m_WIN2_DSP_WIDTH1 (0xfff<<0) +#define m_WIN2_DSP_HEIGHT1 (0xfff<<16) + +#define WIN2_DSP_ST1 (0x00d8) +#define v_WIN2_DSP_XST1(x) (((x)&0x1fff)<<0) +#define v_WIN2_DSP_YST1(x) (((x)&0x1fff)<<16) + +#define m_WIN2_DSP_XST1 (0x1fff<<0) +#define m_WIN2_DSP_YST1 (0x1fff<<16) + +#define WIN2_SRC_ALPHA_CTRL (0x00dc) +#define v_WIN2_SRC_ALPHA_EN(x) (((x)&1)<<0) +#define v_WIN2_SRC_COLOR_M0(x) (((x)&1)<<1) +#define v_WIN2_SRC_ALPHA_M0(x) (((x)&1)<<2) +#define v_WIN2_SRC_BLEND_M0(x) (((x)&3)<<3) +#define v_WIN2_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) +#define v_WIN2_SRC_FACTOR_M0(x) (((x)&7)<<5) +#define v_WIN2_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) +#define v_WIN2_FADING_VALUE(x) (((x)&0xff)<<24) + + +#define m_WIN2_SRC_ALPHA_EN (1<<0) +#define m_WIN2_SRC_COLOR_M0 (1<<1) +#define m_WIN2_SRC_ALPHA_M0 (1<<2) +#define m_WIN2_SRC_BLEND_M0 (3<<3) +#define m_WIN2_SRC_ALPHA_CAL_M0 (1<<5) +#define m_WIN2_SRC_FACTOR_M0 (7<<6) +#define m_WIN2_SRC_GLOBAL_ALPHA (0xff<<16) +#define m_WIN2_FADING_VALUE (0xff<<24) + +#define WIN2_MST2 (0x00e0) +#define WIN2_DSP_INFO2 (0x00e4) +#define v_WIN2_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) +#define v_WIN2_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) + +#define m_WIN2_DSP_WIDTH2 (0xfff<<0) +#define m_WIN2_DSP_HEIGHT2 (0xfff<<16) + + +#define WIN2_DSP_ST2 (0x00e8) +#define v_WIN2_DSP_XST2(x) (((x)&0x1fff)<<0) +#define v_WIN2_DSP_YST2(x) (((x)&0x1fff)<<16) +#define m_WIN2_DSP_XST2 (0x1fff<<0) +#define m_WIN2_DSP_YST2 (0x1fff<<16) + +#define WIN2_DST_ALPHA_CTRL (0x00ec) +#define v_WIN2_DST_FACTOR_M0(x) (((x)&7)<<6) +#define m_WIN2_DST_FACTOR_M0 (7<<6) + +#define WIN2_MST3 (0x00f0) +#define WIN2_DSP_INFO3 (0x00f4) +#define v_WIN2_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) +#define v_WIN2_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) +#define m_WIN2_DSP_WIDTH3 (0xfff<<0) +#define m_WIN2_DSP_HEIGHT3 (0xfff<<16) + +#define WIN2_DSP_ST3 (0x00f8) +#define v_WIN2_DSP_XST3(x) (((x)&0x1fff)<<0) +#define v_WIN2_DSP_YST3(x) (((x)&0x1fff)<<16) +#define m_WIN2_DSP_XST3 (0x1fff<<0) +#define m_WIN2_DSP_YST3 (0x1fff<<16) + +#define WIN2_FADING_CTRL (0x00fc) +#define v_WIN2_FADING_OFFSET_R(x) (((x)&0xff)<<0) +#define v_WIN2_FADING_OFFSET_G(x) (((x)&0xff)<<8) +#define v_WIN2_FADING_OFFSET_B(x) (((x)&0xff)<<16) +#define v_WIN2_FADING_EN(x) (((x)&1)<<24) + +#define m_WIN2_FADING_OFFSET_R (0xff<<0) +#define m_WIN2_FADING_OFFSET_G (0xff<<8) +#define m_WIN2_FADING_OFFSET_B (0xff<<16) +#define m_WIN2_FADING_EN (1<<24) + +/*win3 register*/ +#define WIN3_CTRL0 (0x0100) +#define v_WIN3_EN(x) (((x)&1)<<0) +#define v_WIN3_DATA_FMT(x) (((x)&7)<<1) +#define v_WIN3_MST0_EN(x) (((x)&1)<<4) +#define v_WIN3_MST1_EN(x) (((x)&1)<<5) +#define v_WIN3_MST2_EN(x) (((x)&1)<<6) +#define v_WIN3_MST3_EN(x) (((x)&1)<<7) +#define v_WIN3_INTERLACE_READ(x) (((x)&1)<<8) +#define v_WIN3_NO_OUTSTANDING(x) (((x)&1)<<9) +#define v_WIN3_CSC_MODE(x) (((x)&1)<<10) +#define v_WIN3_RB_SWAP(x) (((x)&1)<<12) +#define v_WIN3_ALPHA_SWAP(x) (((x)&1)<<13) +#define v_WIN3_ENDIAN_MODE(x) (((x)&1)<<14) +#define v_WIN3_LUT_EN(x) (((x)&1)<<18) + +#define m_WIN3_EN (1<<0) +#define m_WIN3_DATA_FMT (7<<1) +#define m_WIN3_MST0_EN (1<<4) +#define m_WIN3_MST1_EN (1<<5) +#define m_WIN3_MST2_EN (1<<6) +#define m_WIN3_MST3_EN (1<<7) +#define m_WIN3_INTERLACE_READ (1<<8) +#define m_WIN3_NO_OUTSTANDING (1<<9) +#define m_WIN3_CSC_MODE (1<<10) +#define m_WIN3_RB_SWAP (1<<12) +#define m_WIN3_ALPHA_SWAP (1<<13) +#define m_WIN3_ENDIAN_MODE (1<<14) +#define m_WIN3_LUT_EN (1<<18) + + +#define WIN3_CTRL1 (0x0104) +#define v_WIN3_AXI_GATHER_EN(x) (((x)&1)<<0) +#define v_WIN3_AXI_GATHER_NUM(x) (((x)&0xf)<<4) +#define m_WIN3_AXI_GATHER_EN (1<<0) +#define m_WIN3_AXI_GATHER_NUM (0xf<<4) + +#define WIN3_VIR0_1 (0x0108) +#define v_WIN3_VIR_STRIDE0(x) (((x)&0x1fff)<<0) +#define v_WIN3_VIR_STRIDE1(x) (((x)&0x1fff)<<16) +#define m_WIN3_VIR_STRIDE0 (0x1fff<<0) +#define m_WIN3_VIR_STRIDE1 (0x1fff<<16) + +#define WIN3_VIR2_3 (0x010c) +#define v_WIN3_VIR_STRIDE2(x) (((x)&0x1fff)<<0) +#define v_WIN3_VIR_STRIDE3(x) (((x)&0x1fff)<<16) +#define m_WIN3_VIR_STRIDE2 (0x1fff<<0) +#define m_WIN3_VIR_STRIDE3 (0x1fff<<16) + +#define WIN3_MST0 (0x0110) +#define WIN3_DSP_INFO0 (0x0114) +#define v_WIN3_DSP_WIDTH0(x) (((x-1)&0xfff)<<0) +#define v_WIN3_DSP_HEIGHT0(x) (((x-1)&0xfff)<<16) +#define m_WIN3_DSP_WIDTH0 (0xfff<<0) +#define m_WIN3_DSP_HEIGHT0 (0xfff<<16) + +#define WIN3_DSP_ST0 (0x0118) +#define v_WIN3_DSP_XST0(x) (((x)&0x1fff)<<0) +#define v_WIN3_DSP_YST0(x) (((x)&0x1fff)<<16) +#define m_WIN3_DSP_XST0 (0x1fff<<0) +#define m_WIN3_DSP_YST0 (0x1fff<<16) + +#define WIN3_COLOR_KEY (0x011c) +#define v_WIN3_COLOR_KEY(x) (((x)&0xffffff)<<0) +#define v_WIN3_KEY_EN(x) (((x)&1)<<24) +#define m_WIN3_COLOR_KEY (0xffffff<<0) +#define m_WIN3_KEY_EN ((u32)1<<24) + +#define WIN3_MST1 (0x0120) +#define WIN3_DSP_INFO1 (0x0124) +#define v_WIN3_DSP_WIDTH1(x) (((x-1)&0xfff)<<0) +#define v_WIN3_DSP_HEIGHT1(x) (((x-1)&0xfff)<<16) +#define m_WIN3_DSP_WIDTH1 (0xfff<<0) +#define m_WIN3_DSP_HEIGHT1 (0xfff<<16) + +#define WIN3_DSP_ST1 (0x0128) +#define v_WIN3_DSP_XST1(x) (((x)&0x1fff)<<0) +#define v_WIN3_DSP_YST1(x) (((x)&0x1fff)<<16) +#define m_WIN3_DSP_XST1 (0x1fff<<0) +#define m_WIN3_DSP_YST1 (0x1fff<<16) + +#define WIN3_SRC_ALPHA_CTRL (0x012c) +#define v_WIN3_SRC_ALPHA_EN(x) (((x)&1)<<0) +#define v_WIN3_SRC_COLOR_M0(x) (((x)&1)<<1) +#define v_WIN3_SRC_ALPHA_M0(x) (((x)&1)<<2) +#define v_WIN3_SRC_BLEND_M0(x) (((x)&3)<<3) +#define v_WIN3_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) +#define v_WIN3_SRC_FACTOR_M0(x) (((x)&7)<<6) +#define v_WIN3_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) +#define v_WIN3_FADING_VALUE(x) (((x)&0xff)<<24) + +#define m_WIN3_SRC_ALPHA_EN (1<<0) +#define m_WIN3_SRC_COLOR_M0 (1<<1) +#define m_WIN3_SRC_ALPHA_M0 (1<<2) +#define m_WIN3_SRC_BLEND_M0 (3<<3) +#define m_WIN3_SRC_ALPHA_CAL_M0 (1<<5) +#define m_WIN3_SRC_FACTOR_M0 (7<<6) +#define m_WIN3_SRC_GLOBAL_ALPHA (0xff<<16) +#define m_WIN3_FADING_VALUE (0xff<<24) + +#define WIN3_MST2 (0x0130) +#define WIN3_DSP_INFO2 (0x0134) +#define v_WIN3_DSP_WIDTH2(x) (((x-1)&0xfff)<<0) +#define v_WIN3_DSP_HEIGHT2(x) (((x-1)&0xfff)<<16) +#define m_WIN3_DSP_WIDTH2 (0xfff<<0) +#define m_WIN3_DSP_HEIGHT2 (0xfff<<16) + +#define WIN3_DSP_ST2 (0x0138) +#define v_WIN3_DSP_XST2(x) (((x)&0x1fff)<<0) +#define v_WIN3_DSP_YST2(x) (((x)&0x1fff)<<16) +#define m_WIN3_DSP_XST2 (0x1fff<<0) +#define m_WIN3_DSP_YST2 (0x1fff<<16) + +#define WIN3_DST_ALPHA_CTRL (0x013c) +#define v_WIN3_DST_FACTOR_M0(x) (((x)&7)<<6) +#define m_WIN3_DST_FACTOR_M0 (7<<6) + + +#define WIN3_MST3 (0x0140) +#define WIN3_DSP_INFO3 (0x0144) +#define v_WIN3_DSP_WIDTH3(x) (((x-1)&0xfff)<<0) +#define v_WIN3_DSP_HEIGHT3(x) (((x-1)&0xfff)<<16) +#define m_WIN3_DSP_WIDTH3 (0xfff<<0) +#define m_WIN3_DSP_HEIGHT3 (0xfff<<16) + +#define WIN3_DSP_ST3 (0x0148) +#define v_WIN3_DSP_XST3(x) (((x)&0x1fff)<<0) +#define v_WIN3_DSP_YST3(x) (((x)&0x1fff)<<16) +#define m_WIN3_DSP_XST3 (0x1fff<<0) +#define m_WIN3_DSP_YST3 (0x1fff<<16) + +#define WIN3_FADING_CTRL (0x014c) +#define v_WIN3_FADING_OFFSET_R(x) (((x)&0xff)<<0) +#define v_WIN3_FADING_OFFSET_G(x) (((x)&0xff)<<8) +#define v_WIN3_FADING_OFFSET_B(x) (((x)&0xff)<<16) +#define v_WIN3_FADING_EN(x) (((x)&1)<<24) + +#define m_WIN3_FADING_OFFSET_R (0xff<<0) +#define m_WIN3_FADING_OFFSET_G (0xff<<8) +#define m_WIN3_FADING_OFFSET_B (0xff<<16) +#define m_WIN3_FADING_EN (1<<24) + + +/*hwc register*/ +#define HWC_CTRL0 (0x0150) +#define v_HWC_EN(x) (((x)&1)<<0) +#define v_HWC_DATA_FMT(x) (((x)&7)<<1) +#define v_HWC_MODE(x) (((x)&1)<<4) +#define v_HWC_SIZE(x) (((x)&3)<<5) +#define v_HWC_INTERLACE_READ(x) (((x)&1)<<8) +#define v_HWC_NO_OUTSTANDING(x) (((x)&1)<<9) +#define v_HWC_CSC_MODE(x) (((x)&1)<<10) +#define v_HWC_RB_SWAP(x) (((x)&1)<<12) +#define v_HWC_ALPHA_SWAP(x) (((x)&1)<<13) +#define v_HWC_ENDIAN_MODE(x) (((x)&1)<<14) +#define v_HWC_LUT_EN(x) (((x)&1)<<18) + +#define m_HWC_EN (1<<0) +#define m_HWC_DATA_FMT (7<<1) +#define m_HWC_MODE (1<<4) +#define m_HWC_SIZE (3<<5) +#define m_HWC_INTERLACE_READ (1<<8) +#define m_HWC_NO_OUTSTANDING (1<<9) +#define m_HWC_CSC_MODE (1<<10) +#define m_HWC_RB_SWAP (1<<12) +#define m_HWC_ALPHA_SWAP (1<<13) +#define m_HWC_ENDIAN_MODE (1<<14) +#define m_HWC_LUT_EN (1<<18) + + +#define HWC_CTRL1 (0x0154) +#define v_HWC_AXI_GATHER_EN(x) (((x)&1)<<0) +#define v_HWC_AXI_GATHER_NUM(x) (((x)&7)<<4) +#define m_HWC_AXI_GATHER_EN (1<<0) +#define m_HWC_AXI_GATHER_NUM (7<<4) + +#define HWC_MST (0x0158) +#define HWC_DSP_ST (0x015c) +#define v_HWC_DSP_XST3(x) (((x)&0x1fff)<<0) +#define v_HWC_DSP_YST3(x) (((x)&0x1fff)<<16) +#define m_HWC_DSP_XST3 (0x1fff<<0) +#define m_HWC_DSP_YST3 (0x1fff<<16) + +#define HWC_SRC_ALPHA_CTRL (0x0160) +#define v_HWC_SRC_ALPHA_EN(x) (((x)&1)<<0) +#define v_HWC_SRC_COLOR_M0(x) (((x)&1)<<1) +#define v_HWC_SRC_ALPHA_M0(x) (((x)&1)<<2) +#define v_HWC_SRC_BLEND_M0(x) (((x)&3)<<3) +#define v_HWC_SRC_ALPHA_CAL_M0(x) (((x)&1)<<5) +#define v_HWC_SRC_FACTOR_M0(x) (((x)&7)<<6) +#define v_HWC_SRC_GLOBAL_ALPHA(x) (((x)&0xff)<<16) +#define v_HWC_FADING_VALUE(x) (((x)&0xff)<<24) + +#define m_HWC_SRC_ALPHA_EN (1<<0) +#define m_HWC_SRC_COLOR_M0 (1<<1) +#define m_HWC_SRC_ALPHA_M0 (1<<2) +#define m_HWC_SRC_BLEND_M0 (3<<3) +#define m_HWC_SRC_ALPHA_CAL_M0 (1<<5) +#define m_HWC_SRC_FACTOR_M0 (7<<6) +#define m_HWC_SRC_GLOBAL_ALPHA (0xff<<16) +#define m_HWC_FADING_VALUE (0xff<<24) + +#define HWC_DST_ALPHA_CTRL (0x0164) +#define v_HWC_DST_FACTOR_M0(x) (((x)&7)<<6) +#define m_HWC_DST_FACTOR_M0 (7<<6) + + +#define HWC_FADING_CTRL (0x0168) +#define v_HWC_FADING_OFFSET_R(x) (((x)&0xff)<<0) +#define v_HWC_FADING_OFFSET_G(x) (((x)&0xff)<<8) +#define v_HWC_FADING_OFFSET_B(x) (((x)&0xff)<<16) +#define v_HWC_FADING_EN(x) (((x)&1)<<24) + +#define m_HWC_FADING_OFFSET_R (0xff<<0) +#define m_HWC_FADING_OFFSET_G (0xff<<8) +#define m_HWC_FADING_OFFSET_B (0xff<<16) +#define m_HWC_FADING_EN (1<<24) + +/*post process register*/ +#define POST_DSP_HACT_INFO (0x0170) +#define v_DSP_HACT_END_POST(x) (((x)&0x1fff)<<0) +#define v_DSP_HACT_ST_POST(x) (((x)&0x1fff)<<16) +#define m_DSP_HACT_END_POST (0x1fff<<0) +#define m_DSP_HACT_ST_POST (0x1fff<<16) + +#define POST_DSP_VACT_INFO (0x0174) +#define v_DSP_VACT_END_POST(x) (((x)&0x1fff)<<0) +#define v_DSP_VACT_ST_POST(x) (((x)&0x1fff)<<16) +#define m_DSP_VACT_END_POST (0x1fff<<0) +#define m_DSP_VACT_ST_POST (0x1fff<<16) + +#define POST_SCL_FACTOR_YRGB (0x0178) +#define v_POST_HS_FACTOR_YRGB(x) (((x)&0xffff)<<0) +#define v_POST_VS_FACTOR_YRGB(x) (((x)&0xffff)<<16) +#define m_POST_HS_FACTOR_YRGB (0xffff<<0) +#define m_POST_VS_FACTOR_YRGB (0xffff<<16) + +#define POST_SCL_CTRL (0x0180) +#define v_POST_HOR_SD_EN(x) (((x)&1)<<0) +#define v_POST_VER_SD_EN(x) (((x)&1)<<1) + +#define m_POST_HOR_SD_EN (0x1<<0) +#define m_POST_VER_SD_EN (0x1<<1) + +#define POST_DSP_VACT_INFO_F1 (0x0184) +#define v_DSP_VACT_END_POST_F1(x) (((x)&0x1fff)<<0) +#define v_DSP_VACT_ST_POST_F1(x) (((x)&0x1fff)<<16) + +#define m_DSP_VACT_END_POST_F1 (0x1fff<<0) +#define m_DSP_VACT_ST_POST_F1 (0x1fff<<16) + +#define DSP_HTOTAL_HS_END (0x0188) +#define v_DSP_HS_PW(x) (((x)&0x1fff)<<0) +#define v_DSP_HTOTAL(x) (((x)&0x1fff)<<16) +#define m_DSP_HS_PW (0x1fff<<0) +#define m_DSP_HTOTAL (0x1fff<<16) + +#define DSP_HACT_ST_END (0x018c) +#define v_DSP_HACT_END(x) (((x)&0x1fff)<<0) +#define v_DSP_HACT_ST(x) (((x)&0x1fff)<<16) +#define m_DSP_HACT_END (0x1fff<<0) +#define m_DSP_HACT_ST (0x1fff<<16) + +#define DSP_VTOTAL_VS_END (0x0190) +#define v_DSP_VS_PW(x) (((x)&0x1fff)<<0) +#define v_DSP_VTOTAL(x) (((x)&0x1fff)<<16) +#define m_DSP_VS_PW (0x1fff<<0) +#define m_DSP_VTOTAL (0x1fff<<16) + +#define DSP_VACT_ST_END (0x0194) +#define v_DSP_VACT_END(x) (((x)&0x1fff)<<0) +#define v_DSP_VACT_ST(x) (((x)&0x1fff)<<16) +#define m_DSP_VACT_END (0x1fff<<0) +#define m_DSP_VACT_ST (0x1fff<<16) + +#define DSP_VS_ST_END_F1 (0x0198) +#define v_DSP_VS_END_F1(x) (((x)&0x1fff)<<0) +#define v_DSP_VS_ST_F1(x) (((x)&0x1fff)<<16) +#define m_DSP_VS_END_F1 (0x1fff<<0) +#define m_DSP_VS_ST_F1 (0x1fff<<16) + +#define DSP_VACT_ST_END_F1 (0x019c) +#define v_DSP_VACT_END_F1(x) (((x)&0x1fff)<<0) +#define v_DSP_VAC_ST_F1(x) (((x)&0x1fff)<<16) +#define m_DSP_VACT_END_F1 (0x1fff<<0) +#define m_DSP_VAC_ST_F1 (0x1fff<<16) + + +/*pwm register*/ +#define PWM_CTRL (0x01a0) +#define v_PWM_EN(x) (((x)&1)<<0) +#define v_PWM_MODE(x) (((x)&3)<<1) + +#define v_DUTY_POL(x) (((x)&1)<<3) +#define v_INACTIVE_POL(x) (((x)&1)<<4) +#define v_OUTPUT_MODE(x) (((x)&1)<<5) +#define v_BL_EN(x) (((x)&1)<<8) +#define v_CLK_SEL(x) (((x)&1)<<9) +#define v_PRESCALE(x) (((x)&7)<<12) +#define v_SCALE(x) (((x)&0xff)<<16) +#define v_RPT(x) (((x)&0xff)<<24) + +#define m_PWM_EN (1<<0) +#define m_PWM_MODE (3<<1) + +#define m_DUTY_POL (1<<3) +#define m_INACTIVE_POL (1<<4) +#define m_OUTPUT_MODE (1<<5) +#define m_BL_EN (1<<8) +#define m_CLK_SEL (1<<9) +#define m_PRESCALE (7<<12) +#define m_SCALE (0xff<<16) +#define m_RPT ((u32)0xff<<24) + +#define PWM_PERIOD_HPR (0x01a4) +#define PWM_DUTY_LPR (0x01a8) +#define PWM_CNT (0x01ac) + +/*BCSH register*/ +#define BCSH_COLOR_BAR (0x01b0) +#define v_BCSH_EN(x) (((x)&1)<<0) +#define v_BCSH_COLOR_BAR_Y(x) (((x)&0x3ff)<<2) +#define v_BCSH_COLOR_BAR_U(x) (((x)&0x3ff)<<12) +#define v_BCSH_COLOR_BAR_V(x) (((x)&0x3ff)<<22) + +#define m_BCSH_EN (1<<0) +#define m_BCSH_COLOR_BAR_Y (0x3ff<<2) +#define m_BCSH_COLOR_BAR_U (0x3ff<<12) +#define m_BCSH_COLOR_BAR_V ((u32)0x3ff<<22) + +#define BCSH_BCS (0x01b4) +#define v_BCSH_BRIGHTNESS(x) (((x)&0xff)<<0) +#define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8) +#define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20) +#define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30) + +#define m_BCSH_BRIGHTNESS (0xff<<0) +#define m_BCSH_CONTRAST (0x1ff<<8) +#define m_BCSH_SAT_CON (0x3ff<<20) +#define m_BCSH_OUT_MODE ((u32)0x3<<30) + + +#define BCSH_H (0x01b8) +#define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0) +#define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16) + +#define m_BCSH_SIN_HUE (0x1ff<<0) +#define m_BCSH_COS_HUE (0x1ff<<16) + +#define CABC_CTRL0 (0x01c0) +#define v_CABC_EN(x) (((x)&1)<<0) +#define v_CABC_CALC_PIXEL_NUM(x) (((x)&0x7fffff)<<1) +#define v_CABC_STAGE_UP(x) (((x)&0xff)<<24) +#define m_CABC_EN (1<<0) +#define m_CABC_CALC_PIXEL_NUM (0x7fffff<<1) +#define m_CABC_STAGE_UP (0xff<<24) + + +#define CABC_CTRL1 (0x01c4) +#define v_CABC_TOTAL_NUM(x) (((x)&0x7fffff)<<1) +#define v_CABC_STAGE_DOWN(x) (((x)&0xff)<<24) +#define m_CABC_TOTAL_NUM (0x7fffff<<1) +#define m_CABC_STAGE_DOWN (0xff<<24) + +#define CABC_GAUSS_LINE0_0 (0x01c8) +#define v_CABC_T_LINE0_0(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE0_1(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE0_2(x) (((x)&0xff)<<16) +#define v_CABC_T_LINE0_3(x) (((x)&0xff)<<24) +#define m_CABC_T_LINE0_0 (0xff<<0) +#define m_CABC_T_LINE0_1 (0xff<<8) +#define m_CABC_T_LINE0_2 (0xff<<16) +#define m_CABC_T_LINE0_3 ((u32)0xff<<24) + +#define CABC_GAUSS_LINE0_1 (0x01cc) +#define v_CABC_T_LINE0_4(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE0_5(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE0_6(x) (((x)&0xff)<<16) +#define m_CABC_T_LINE0_4 (0xff<<0) +#define m_CABC_T_LINE0_5 (0xff<<8) +#define m_CABC_T_LINE0_6 (0xff<<16) + + +#define CABC_GAUSS_LINE1_0 (0x01d0) +#define v_CABC_T_LINE1_0(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE1_1(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE1_2(x) (((x)&0xff)<<16) +#define v_CABC_T_LINE1_3(x) (((x)&0xff)<<24) +#define m_CABC_T_LINE1_0 (0xff<<0) +#define m_CABC_T_LINE1_1 (0xff<<8) +#define m_CABC_T_LINE1_2 (0xff<<16) +#define m_CABC_T_LINE1_3 ((u32)0xff<<24) + +#define CABC_GAUSS_LINE1_1 (0x01d4) +#define v_CABC_T_LINE1_4(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE1_5(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE1_6(x) (((x)&0xff)<<16) +#define m_CABC_T_LINE1_4 (0xff<<0) +#define m_CABC_T_LINE1_5 (0xff<<8) +#define m_CABC_T_LINE1_6 (0xff<<16) + +#define CABC_GAUSS_LINE2_0 (0x01d8) +#define v_CABC_T_LINE2_0(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE2_1(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE2_2(x) (((x)&0xff)<<16) +#define v_CABC_T_LINE2_3(x) (((x)&0xff)<<24) +#define m_CABC_T_LINE2_0 (0xff<<0) +#define m_CABC_T_LINE2_1 (0xff<<8) +#define m_CABC_T_LINE2_2 (0xff<<16) +#define m_CABC_T_LINE2_3 ((u32)0xff<<24) + +#define CABC_GAUSS_LINE2_1 (0x01dc) +#define v_CABC_T_LINE2_4(x) (((x)&0xff)<<0) +#define v_CABC_T_LINE2_5(x) (((x)&0xff)<<8) +#define v_CABC_T_LINE2_6(x) (((x)&0xff)<<16) +#define m_CABC_T_LINE2_4 (0xff<<0) +#define m_CABC_T_LINE2_5 (0xff<<8) +#define m_CABC_T_LINE2_6 (0xff<<16) + +/*FRC register*/ +#define FRC_LOWER01_0 (0x01e0) +#define v_FRC_LOWER01_FRM0(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER01_FRM1(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER01_FRM0 (0xffff<<0) +#define m_FRC_LOWER01_FRM1 ((u32)0xffff<<16) + +#define FRC_LOWER01_1 (0x01e4) +#define v_FRC_LOWER01_FRM2(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER01_FRM3(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER01_FRM2 (0xffff<<0) +#define m_FRC_LOWER01_FRM3 ((u32)0xffff<<16) + +#define FRC_LOWER10_0 (0x01e8) +#define v_FRC_LOWER10_FRM0(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER10_FRM1(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER10_FRM0 (0xffff<<0) +#define m_FRC_LOWER10_FRM1 ((u32)0xffff<<16) + +#define FRC_LOWER10_1 (0x01ec) +#define v_FRC_LOWER10_FRM2(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER10_FRM3(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER10_FRM2 (0xffff<<0) +#define m_FRC_LOWER10_FRM3 ((u32)0xffff<<16) + +#define FRC_LOWER11_0 (0x01f0) +#define v_FRC_LOWER11_FRM0(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER11_FRM1(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER11_FRM0 (0xffff<<0) +#define m_FRC_LOWER11_FRM1 ((u32)0xffff<<16) + +#define FRC_LOWER11_1 (0x01f4) +#define v_FRC_LOWER11_FRM2(x) (((x)&0xffff)<<0) +#define v_FRC_LOWER11_FRM3(x) (((x)&0xffff)<<16) +#define m_FRC_LOWER11_FRM2 (0xffff<<0) +#define m_FRC_LOWER11_FRM3 ((u32)0xffff<<16) + +#define MMU_DTE_ADDR (0x0300) +#define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0) +#define m_MMU_DTE_ADDR (0xffffffff<<0) + +#define MMU_STATUS (0x0304) +#define v_PAGING_ENABLED(x) (((x)&1)<<0) +#define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1) +#define v_STAIL_ACTIVE(x) (((x)&1)<<2) +#define v_MMU_IDLE(x) (((x)&1)<<3) +#define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4) +#define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5) +#define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6) +#define m_PAGING_ENABLED (1<<0) +#define m_PAGE_FAULT_ACTIVE (1<<1) +#define m_STAIL_ACTIVE (1<<2) +#define m_MMU_IDLE (1<<3) +#define m_REPLAY_BUFFER_EMPTY (1<<4) +#define m_PAGE_FAULT_IS_WRITE (1<<5) +#define m_PAGE_FAULT_BUS_ID (0x1f<<6) + +#define MMU_COMMAND (0x0308) +#define v_MMU_CMD(x) (((x)&0x3)<<0) +#define m_MMU_CMD (0x3<<0) + +#define MMU_PAGE_FAULT_ADDR (0x030c) +#define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0) +#define m_PAGE_FAULT_ADDR (0xffffffff<<0) + +#define MMU_ZAP_ONE_LINE (0x0310) +#define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0) +#define m_MMU_ZAP_ONE_LINE (0xffffffff<<0) + +#define MMU_INT_RAWSTAT (0x0314) +#define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0) +#define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1) +#define m_PAGE_FAULT_RAWSTAT (1<<0) +#define m_READ_BUS_ERROR_RAWSTAT (1<<1) + +#define MMU_INT_CLEAR (0x0318) +#define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0) +#define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1) +#define m_PAGE_FAULT_CLEAR (1<<0) +#define m_READ_BUS_ERROR_CLEAR (1<<1) + +#define MMU_INT_MASK (0x031c) +#define v_PAGE_FAULT_MASK(x) (((x)&1)<<0) +#define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1) +#define m_PAGE_FAULT_MASK (1<<0) +#define m_READ_BUS_ERROR_MASK (1<<1) + +#define MMU_INT_STATUS (0x0320) +#define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0) +#define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1) +#define m_PAGE_FAULT_STATUS (1<<0) +#define m_READ_BUS_ERROR_STATUS (1<<1) + +#define MMU_AUTO_GATING (0x0324) +#define v_MMU_AUTO_GATING(x) (((x)&1)<<0) +#define m_MMU_AUTO_GATING (1<<0) + +#define WIN2_LUT_ADDR (0x0400) +#define WIN3_LUT_ADDR (0x0800) +#define HWC_LUT_ADDR (0x0c00) +#define GAMMA_LUT_ADDR (0x1000) +#define MCU_BYPASS_WPORT (0x2200) +#define MCU_BYPASS_RPORT (0x2300) + +#define PWM_MODE_ONE_SHOT (0x0) +#define PWM_MODE_CONTINUOUS (0x1) +#define PWM_MODE_CAPTURE (0x2) + +struct lcdc_device{ + int id; + struct rk_lcdc_driver driver; + struct device *dev; + struct rk_screen *screen; + + void __iomem *regs; + void *regsbak; /*back up reg*/ + u32 reg_phy_base; /* physical basic address of lcdc register*/ + u32 len; /* physical map length of lcdc register*/ + spinlock_t reg_lock; /*one time only one process allowed to config the register*/ + + int __iomem *dsp_lut_addr_base; + + int prop; /*used for primary or extended display device*/ + bool pre_init; + bool pwr18; /*if lcdc use 1.8v power supply*/ + bool clk_on; /*if aclk or hclk is closed ,acess to register is not allowed*/ + u8 atv_layer_cnt; /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/ + + + unsigned int irq; + + struct clk *pd; /*lcdc power domain*/ + struct clk *hclk; /*lcdc AHP clk*/ + struct clk *dclk; /*lcdc dclk*/ + struct clk *aclk; /*lcdc share memory frequency*/ + u32 pixclock; + + u32 standby; /*1:standby,0:wrok*/ +}; + +struct alpha_config{ + u8 src_alpha_mode; /*win0_src_alpha_m0*/ + u8 src_global_alpha_val; /*win0_src_global_alpha*/ + u8 src_global_alpha_mode;/*win0_src_blend_m0*/ + u8 src_alpha_sel; /*win0_src_alpha_cal_m0*/ + u8 src_color_mode; /*win0_src_color_m0*/ + u8 src_factor_mode; /*win0_src_factor_m0*/ + u8 dst_factor_mode; /*win0_dst_factor_m0*/ +}; + +static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v) +{ + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + *_pv = v; + writel_relaxed(v,lcdc_dev->regs+offset); +} + +static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset) +{ + u32 v; + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + v = readl_relaxed(lcdc_dev->regs+offset); + *_pv = v; + return v; +} + +static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) +{ + u32 _v = readl_relaxed(lcdc_dev->regs+offset); + _v &= msk; + return (_v >> msk); +} + +static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) +{ + u32* _pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) |= msk; + writel_relaxed(*_pv,lcdc_dev->regs + offset); +} + +static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk) +{ + u32* _pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) &= (~msk); + writel_relaxed(*_pv,lcdc_dev->regs + offset); +} + +static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v) +{ + u32 *_pv = (u32*)lcdc_dev->regsbak; + _pv += (offset >> 2); + (*_pv) &= (~msk); + (*_pv) |= v; + writel_relaxed(*_pv,lcdc_dev->regs+offset); +} + +static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev) +{ + writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); + dsb(); +} + +#define CUBIC_PRECISE 0 +#define CUBIC_SPLINE 1 +#define CUBIC_CATROM 2 +#define CUBIC_MITCHELL 3 + +#define CUBIC_MODE_SELETION CUBIC_PRECISE + +/*****************************************************************************************************/ +#define SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT 12 /* 4.12*/ +#define SCALE_FACTOR_BILI_DN_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT))) + +#define SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT 16 /* 0.16*/ + +#define SCALE_FACTOR_AVRG_FIXPOINT_SHIFT 16 /*0.16*/ +#define SCALE_FACTOR_AVRG_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))) + +#define SCALE_FACTOR_BIC_FIXPOINT_SHIFT 16 /* 0.16*/ +#define SCALE_FACTOR_BIC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FACTOR_BIC_FIXPOINT_SHIFT))) + +#define SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT 12 /*NONE SCALE,vsd_bil*/ +#define SCALE_FACTOR_VSDBIL_FIXPOINT_SHIFT 12 /*VER SCALE DOWN BIL*/ + +/*****************************************************************************************************/ + +/*#define GET_SCALE_FACTOR_BILI(src, dst) ((((src) - 1) << SCALE_FACTOR_BILI_FIXPOINT_SHIFT) / ((dst) - 1))*/ +/*#define GET_SCALE_FACTOR_BIC(src, dst) ((((src) - 1) << SCALE_FACTOR_BIC_FIXPOINT_SHIFT) / ((dst) - 1))*/ +/*modified by hpz*/ +#define GET_SCALE_FACTOR_BILI_DN(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_DN_FIXPOINT_SHIFT-1)) / ((dst) - 1)) +#define GET_SCALE_FACTOR_BILI_UP(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BILI_UP_FIXPOINT_SHIFT-1)) / ((dst) - 1)) +#define GET_SCALE_FACTOR_BIC(src, dst) ((((src)*2 - 3) << (SCALE_FACTOR_BIC_FIXPOINT_SHIFT-1)) / ((dst) - 1)) + +/*****************************************************************/ +/*NOTE: hardwareΪ½ÚÊ¡¿ªÏú, srcHÏȳéÐеõ½ (srcH+vScaleDnMult-1)/vScaleDnMult; È»ºóËõ·Å*/ +#define GET_SCALE_DN_ACT_HEIGHT(srcH, vScaleDnMult) (((srcH)+(vScaleDnMult)-1)/(vScaleDnMult)) + +/*#define VSKIP_MORE_PRECISE*/ + +#ifdef VSKIP_MORE_PRECISE +#define MIN_SCALE_FACTOR_AFTER_VSKIP 1.5f +#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ + (GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) +#else +#define MIN_SCALE_FACTOR_AFTER_VSKIP 1 +#define GET_SCALE_FACTOR_BILI_DN_VSKIP(srcH, dstH, vScaleDnMult) \ + ((GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)) == (dstH))\ + ? (GET_SCALE_FACTOR_BILI_DN((srcH), (dstH))/(vScaleDnMult))\ + : GET_SCALE_FACTOR_BILI_DN(GET_SCALE_DN_ACT_HEIGHT((srcH), (vScaleDnMult)), (dstH))) +#endif +/*****************************************************************/ + + +/*ScaleFactor must >= dst/src, or pixels at end of line may be unused*/ +/*ScaleFactor must < dst/(src-1), or dst buffer may overflow*/ +/*avrg old code: ((((dst) << SCALE_FACTOR_AVRG_FIXPOINT_SHIFT))/((src) - 1)) /*hxx_chg/*src*/ +/*modified by hpz:*/ +#define GET_SCALE_FACTOR_AVRG(src, dst) ((((dst) << (SCALE_FACTOR_AVRG_FIXPOINT_SHIFT+1)))/(2*(src) - 1)) + +/*****************************************************************************************************/ +/*Scale Coordinate Accumulate, x.16*/ +#define SCALE_COOR_ACC_FIXPOINT_SHIFT 16 +#define SCALE_COOR_ACC_FIXPOINT_ONE (1 << SCALE_COOR_ACC_FIXPOINT_SHIFT) +#define SCALE_COOR_ACC_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_COOR_ACC_FIXPOINT_SHIFT))) +#define SCALE_COOR_ACC_FIXPOINT_REVERT(x) ((((x) >> (SCALE_COOR_ACC_FIXPOINT_SHIFT-1)) + 1) >> 1) + +#define SCALE_GET_COOR_ACC_FIXPOINT(scaleFactor, factorFixpointShift) \ + ((scaleFactor) << (SCALE_COOR_ACC_FIXPOINT_SHIFT - (factorFixpointShift))) + + +/*****************************************************************************************************/ +/*CoarsePart of Scale Coordinate Accumulate, used for pixel mult-add factor, 0.8*/ +#define SCALE_FILTER_FACTOR_FIXPOINT_SHIFT 8 +#define SCALE_FILTER_FACTOR_FIXPOINT_ONE (1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT) +#define SCALE_FILTER_FACTOR_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))) +#define SCALE_FILTER_FACTOR_FIXPOINT_REVERT(x) ((((x) >> (SCALE_FILTER_FACTOR_FIXPOINT_SHIFT-1)) + 1) >> 1) + +#define SCALE_GET_FILTER_FACTOR_FIXPOINT(coorAccumulate, coorAccFixpointShift) \ + (((coorAccumulate)>>((coorAccFixpointShift)-SCALE_FILTER_FACTOR_FIXPOINT_SHIFT))&(SCALE_FILTER_FACTOR_FIXPOINT_ONE-1)) + +#define SCALE_OFFSET_FIXPOINT_SHIFT 8 +#define SCALE_OFFSET_FIXPOINT(x) ((INT32)((x)*(1 << SCALE_OFFSET_FIXPOINT_SHIFT))) + +u32 getHardWareVSkipLines(u32 srcH, u32 dstH) +{ + u32 vScaleDnMult; + + if(srcH >= (u32)(4*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) + { + vScaleDnMult = 4; + } + else if(srcH >= (u32)(2*dstH*MIN_SCALE_FACTOR_AFTER_VSKIP)) + { + vScaleDnMult = 2; + } + else + { + vScaleDnMult = 1; + } + + return vScaleDnMult; +} + + +enum lb_mode { + LB_YUV_3840X5 = 0x0, + LB_YUV_2560X8 = 0x1, + LB_RGB_3840X2 = 0x2, + LB_RGB_2560X4 = 0x3, + LB_RGB_1920X5 = 0x4, + LB_RGB_1280X8 = 0x5 +}; + +enum sacle_up_mode { + SCALE_UP_BIL = 0x0, + SCALE_UP_BIC = 0x1 +}; + +enum scale_down_mode { + SCALE_DOWN_BIL = 0x0, + SCALE_DOWN_AVG = 0x1 +}; + +/*ALPHA BLENDING MODE*/ +enum alpha_mode { /* Fs Fd */ + AB_USER_DEFINE = 0x0, + AB_CLEAR = 0x1,/* 0 0*/ + AB_SRC = 0x2,/* 1 0*/ + AB_DST = 0x3,/* 0 1 */ + AB_SRC_OVER = 0x4,/* 1 1-As''*/ + AB_DST_OVER = 0x5,/* 1-Ad'' 1*/ + AB_SRC_IN = 0x6, + AB_DST_IN = 0x7, + AB_SRC_OUT = 0x8, + AB_DST_OUT = 0x9, + AB_SRC_ATOP = 0xa, + AB_DST_ATOP = 0xb, + XOR = 0xc, + AB_SRC_OVER_GLOBAL = 0xd +}; /*alpha_blending_mode*/ + +enum src_alpha_mode { + AA_STRAIGHT = 0x0, + AA_INVERSE = 0x1 +};/*src_alpha_mode*/ + +enum global_alpha_mode { + AA_GLOBAL = 0x0, + AA_PER_PIX = 0x1, + AA_PER_PIX_GLOBAL = 0x2 +};/*src_global_alpha_mode*/ + +enum src_alpha_sel { + AA_SAT = 0x0, + AA_NO_SAT = 0x1 +};/*src_alpha_sel*/ + +enum src_color_mode { + AA_SRC_PRE_MUL = 0x0, + AA_SRC_NO_PRE_MUL = 0x1 +};/*src_color_mode*/ + +enum factor_mode { + AA_ZERO = 0x0, + AA_ONE = 0x1, + AA_SRC = 0x2, + AA_SRC_INVERSE = 0x3, + AA_SRC_GLOBAL = 0x4 +};/*src_factor_mode && dst_factor_mode*/ +#endif diff --git a/drivers/video/rockchip/rk_fb.c b/drivers/video/rockchip/rk_fb.c index 93ea7ec1c2f5..9e0c20506c91 100755 --- a/drivers/video/rockchip/rk_fb.c +++ b/drivers/video/rockchip/rk_fb.c @@ -87,7 +87,7 @@ int rk_fb_pixel_width(int data_format) static int rk_fb_data_fmt(int data_format,int bits_per_pixel) { int fb_data_fmt; - if(bits_per_pixel == 0){ + if(data_format){ switch(data_format){ case HAL_PIXEL_FORMAT_RGBX_8888: fb_data_fmt = XBGR888; @@ -253,6 +253,7 @@ int rk_fb_video_mode_from_timing(const struct display_timing *dt, screen->type = dt->screen_type; screen->lvds_format = dt->lvds_format; screen->face = dt->face; + if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) screen->pin_dclk = 1; else @@ -293,7 +294,10 @@ int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv) "vactive:%d\n" "vback_porch:%d\n" "vfront_porch:%d\n" - "vsync_len:%d\n", + "vsync_len:%d\n" + "screen_type:%d\n" + "lvds_format:%d\n" + "face:%d\n", dt->pixelclock.typ, dt->hactive.typ, dt->hback_porch.typ, @@ -302,7 +306,10 @@ int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv) dt->vactive.typ, dt->vback_porch.typ, dt->vfront_porch.typ, - dt->vsync_len.typ); + dt->vsync_len.typ, + dt->screen_type, + dt->lvds_format, + dt->face); return 0; } @@ -772,9 +779,6 @@ static int rk_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) uv_y_off = yoffset; fix->line_length = stride<<2; break; - default: - printk(KERN_ERR "%s:un supported format:0x%x\n", __func__, data_format); - return -EINVAL; } // x y mirror ,jump line @@ -807,10 +811,6 @@ static int rk_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) win->area[0].y_offset = yoffset*xvir + xoffset; win->area[0].c_offset = yoffset*2*xvir + (xoffset<<1); break; - default: - printk(KERN_ERR "%s un supported format:0x%x\n", - __func__, data_format); - return -EINVAL; } win->area[0].smem_start = fix->smem_start; win->area[0].cbr_start = fix->smem_start + xvir * yvir; @@ -1285,7 +1285,7 @@ static int rk_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg int num_buf; /*buffer_number*/ int ret; struct rk_fb_win_cfg_data win_data; - unsigned int dsp_addr[2]; + unsigned int dsp_addr[4]; int list_stat; int win_id = dev_drv->ops->fb_get_win_id(dev_drv, info->fix.id); @@ -1975,8 +1975,8 @@ int rk_fb_switch_screen(struct rk_screen *screen , int enable, int lcdc_id) int ret; int win_id; - if (rk_fb->disp_mode != DUAL) - rk29_backlight_set(0); + //if (rk_fb->disp_mode != DUAL) + // rk29_backlight_set(0); sprintf(name, "lcdc%d", lcdc_id); @@ -2092,8 +2092,8 @@ int rk_fb_switch_screen(struct rk_screen *screen , int enable, int lcdc_id) } } - if (rk_fb->disp_mode != DUAL) - rk29_backlight_set(1); + //if (rk_fb->disp_mode != DUAL) + // rk29_backlight_set(1); hdmi_switch_complete = enable; return 0; diff --git a/include/linux/rk_fb.h b/include/linux/rk_fb.h index f711e1f500fd..b20947b68857 100755 --- a/include/linux/rk_fb.h +++ b/include/linux/rk_fb.h @@ -96,6 +96,7 @@ extern bool rk_fb_poll_wait_frame_complete(void); #define OUT_CCIR656 6 #define OUT_S888 8 #define OUT_S888DUMY 12 +#define OUT_RGB_AAA 15 #define OUT_P16BPP4 24 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23 #define OUT_D888_P565 0x22 @@ -538,19 +539,5 @@ extern int rk_fb_calc_fps(struct rk_screen * screen, u32 pixclock); extern void rk_fd_fence_wait(struct rk_lcdc_driver *dev_drv, struct sync_fence *fence); extern void rk_fb_free_dma_buf(struct rk_fb_reg_win_data *reg_win_data); -#if defined(CONFIG_BACKLIGHT_RK29_BL) -void rk29_backlight_set(bool on); -bool rk29_get_backlight_status(void); -#else -static void rk29_backlight_set(bool on) -{ - while (0) ; -} - -static bool rk29_get_backlight_status(void) -{ - return false; -} -#endif #endif diff --git a/include/linux/rk_screen.h b/include/linux/rk_screen.h index f03ab5ce2cc7..4888ee88379f 100755 --- a/include/linux/rk_screen.h +++ b/include/linux/rk_screen.h @@ -67,6 +67,7 @@ struct rk_screen { u32 post_ysize; u16 x_mirror; u16 y_mirror; + int interlace; u16 width; u16 height; u8 ft; -- 2.34.1