From a7078c4f274e2c2ad431ae9f578624335c81be36 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Fri, 25 Mar 2011 01:09:48 +0000 Subject: [PATCH] Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../ARM/Disassembler/ThumbDisassemblerCore.h | 18 +++++++++--------- test/MC/Disassembler/ARM/thumb-tests.txt | 3 +++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index f9d2bd0d383..c2dd6a1e9e7 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1230,9 +1230,6 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn, return true; } -// LLVM, as of Jan-05-2010, does not output , i.e., Rs, in the asm. -// Whereas the ARM Arch. Manual does not require that t2 = t+1 like in ARM ISA. -// // t2LDRDi8: Rd Rs Rn imm8s4 (offset mode) // t2LDRDpci: Rd Rs imm8s4 (Not decoded, prefer the generic t2LDRDi8 version) // t2STRDi8: Rd Rs Rn imm8s4 (offset mode) @@ -1246,18 +1243,21 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode, if (!OpInfo) return false; assert(NumOps >= 4 - && OpInfo[0].RegClass == ARM::GPRRegClassID - && OpInfo[1].RegClass == ARM::GPRRegClassID - && OpInfo[2].RegClass == ARM::GPRRegClassID + && OpInfo[0].RegClass > 0 + && OpInfo[0].RegClass == OpInfo[1].RegClass + && OpInfo[2].RegClass > 0 && OpInfo[3].RegClass < 0 && "Expect >= 4 operands and first 3 as reg operands"); // Add the operands. - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + unsigned RegClassPair = OpInfo[0].RegClass; + unsigned RegClassBase = OpInfo[2].RegClass; + + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair, decodeRd(insn)))); - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassPair, decodeRs(insn)))); - MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassBase, decodeRn(insn)))); // Finally add (+/-)imm8*4, depending on the U bit. diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 22b1da792b6..666e9f5f47b 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -151,3 +151,6 @@ # CHECK: addw r0, pc, #1050 0x0f 0xf2 0x1a 0x40 + +# CHECK: ldrd r3, r8, [r11, #-60] +0x5b 0xe9 0x0f 0x38 -- 2.34.1