From a733bd2d8fb5449c8e5895281a3be7bceff280d9 Mon Sep 17 00:00:00 2001 From: chenxing Date: Mon, 6 May 2013 21:00:17 +0800 Subject: [PATCH] rk3188: redefine the interface of getting pll flag --- arch/arm/mach-rk30/ddr.c | 8 +++---- arch/arm/mach-rk3188/clock_data.c | 14 ++++-------- arch/arm/plat-rk/efuse.c | 32 +++++++++++++++------------ arch/arm/plat-rk/include/plat/efuse.h | 19 ++++++++++++++-- 4 files changed, 42 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c index cd242744d867..2dba5a41aadd 100755 --- a/arch/arm/mach-rk30/ddr.c +++ b/arch/arm/mach-rk30/ddr.c @@ -22,6 +22,8 @@ #include #include +#include + typedef uint32_t uint32; //#define ENABLE_DDR_CLCOK_GPLL_PATH //for RK3188 @@ -3393,13 +3395,9 @@ void __sramlocalfunc ddr_set_pll_exit_3168(uint32 freq_slew,uint32_t dqstr_value static bool ddr_dpll_status = true; #if defined(CONFIG_ARCH_RK3188) -extern int efuse_readregs(u32 addr, u32 length, u8 *pData); void ddr_get_dpll_status(void) //DPLL fial rerurn 0;DPLL good return 1; { - uint8_t data_buf[32 + 1]; - efuse_readregs(0, 32, data_buf); - - if (data_buf[22] & 0x2) + if (rk_pll_flag() & 0x2) ddr_dpll_status = false; else ddr_dpll_status = true; diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c index 5a43df76eb68..3f9d2420b96e 100755 --- a/arch/arm/mach-rk3188/clock_data.c +++ b/arch/arm/mach-rk3188/clock_data.c @@ -3411,16 +3411,7 @@ static void div_clk_for_pll_init(void) clock_set_max_div(&clk_saradc); } -/************************************for cpll runing checking****************************************/ static u8 pll_flag = 0; -static int pll_get_flag(void) -{ - u8 data_buf[32 + 1]; - efuse_readregs(0, 32, data_buf); - - printk("pll_flag = 0x%02x\n", data_buf[22]); - return data_buf[22] & 0x3; -} static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate) { @@ -3514,7 +3505,10 @@ void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int fl general_pll_clk.set_rate = plus_gpll_clk_set_rate; } - pll_flag = pll_get_flag(); + rk_efuse_init(); + pll_flag = rk_pll_flag(); + printk("CLKDATA_MSG: pll_flag = 0x%02x\n", pll_flag); + if (0 != pll_flag) { CLKDATA_DBG("CPLL=%lu, GPLL=%lu;CPLL CAN NOT LOCK, SET CPLL BY PASS, USE GPLL REPLACE CPLL\n", cpll, gpll); diff --git a/arch/arm/plat-rk/efuse.c b/arch/arm/plat-rk/efuse.c index 57c24df0897d..dcb829515d5e 100644 --- a/arch/arm/plat-rk/efuse.c +++ b/arch/arm/plat-rk/efuse.c @@ -12,25 +12,14 @@ #include #include -/* eFuse controller register */ -#define EFUSE_A_SHIFT (6) -#define EFUSE_A_MASK (0xFF) -//#define EFUSE_PD (1 << 5) -//#define EFUSE_PS (1 << 4) -#define EFUSE_PGENB (1 << 3) //active low -#define EFUSE_LOAD (1 << 2) -#define EFUSE_STROBE (1 << 1) -#define EFUSE_CSB (1 << 0) //active low - -#define REG_EFUSE_CTRL (0x0000) -#define REG_EFUSE_DOUT (0x0004) - #if defined(CONFIG_ARCH_RK3188) #define efuse_readl(offset) readl_relaxed(RK30_EFUSE_BASE + offset) #define efuse_writel(val, offset) writel_relaxed(val, RK30_EFUSE_BASE + offset) #endif -int efuse_readregs(u32 addr, u32 length, u8 *buf) +u8 efuse_buf[32 + 1] = {0, 0}; + +static int efuse_readregs(u32 addr, u32 length, u8 *buf) { #ifndef efuse_readl return 0; @@ -67,3 +56,18 @@ int efuse_readregs(u32 addr, u32 length, u8 *buf) return ret; #endif } + +void rk_efuse_init(void) +{ + efuse_readregs(0x0, 32, efuse_buf); +} + +int rk_pll_flag(void) +{ + return efuse_buf[22] & 0x3; +} + +int rk_leakage_val(void) +{ + return (efuse_buf[22] >> 4) & 0x0f; +} diff --git a/arch/arm/plat-rk/include/plat/efuse.h b/arch/arm/plat-rk/include/plat/efuse.h index 44056f846760..799a4e832961 100644 --- a/arch/arm/plat-rk/include/plat/efuse.h +++ b/arch/arm/plat-rk/include/plat/efuse.h @@ -3,7 +3,22 @@ #include -/* On success, the number of bytes read is returned */ -int efuse_readregs(u32 addr, u32 length, u8 *buf); +/* eFuse controller register */ +#define EFUSE_A_SHIFT (6) +#define EFUSE_A_MASK (0xFF) +//#define EFUSE_PD (1 << 5) +//#define EFUSE_PS (1 << 4) +#define EFUSE_PGENB (1 << 3) //active low +#define EFUSE_LOAD (1 << 2) +#define EFUSE_STROBE (1 << 1) +#define EFUSE_CSB (1 << 0) //active low + +#define REG_EFUSE_CTRL (0x0000) +#define REG_EFUSE_DOUT (0x0004) + +/* Interfaces to get efuse informations */ +void rk_efuse_init(void); +int rk_pll_flag(void); +int rk_leakage_val(void); #endif -- 2.34.1