From a75ce9f5d2236d93c117e861e60e6f3f748c9555 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 24 Dec 2010 07:10:19 +0000 Subject: [PATCH] Minor cleanup related to my latest scheduler changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 69aec439204..b3d05c700ac 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -328,7 +328,7 @@ namespace llvm { /// isInstr - Return true if this SUnit refers to a machine instruction as /// opposed to an SDNode. - bool isInstr() const { return !Node; } + bool isInstr() const { return Instr; } /// setInstr - Assign the instruction for the SUnit. /// This may be used during post-regalloc scheduling. diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index d6368047bcd..a51595f1b06 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -348,7 +348,10 @@ void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { /// Check to see if any of the pending instructions are ready to issue. If /// so, add them to the available queue. void ScheduleDAGRRList::ReleasePending() { - assert(!EnableSchedCycles && "requires --enable-sched-cycles" ); + if (!EnableSchedCycles) { + assert(PendingQueue.empty() && "pending instrs not allowed in this mode"); + return; + } // If the available queue is empty, it is safe to reset MinAvailableCycle. if (AvailableQueue->empty()) @@ -634,8 +637,7 @@ void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { RestoreHazardCheckerBottomUp(); - if (EnableSchedCycles) - ReleasePending(); + ReleasePending(); ++NumBacktracks; } -- 2.34.1