From a8091fbafa42f9a68f5838849c1c8caf59eddf97 Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Fri, 2 Dec 2016 17:34:53 +0800 Subject: [PATCH] drm/rockchip: vop: skip config timing on vblank Change-Id: I7aace5e26f6c9889c9e216f7b7233ec7e5530776 Signed-off-by: Mark Yao --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 4a16d310aac1..d4bf02066b11 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1338,14 +1338,19 @@ static void vop_crtc_enable(struct drm_crtc *crtc) u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start; u16 vact_end = vact_st + vdisplay; + uint32_t version = vop->data->version; uint32_t val; vop_enable(crtc); /* * If dclk rate is zero, mean that scanout is stop, * we don't need wait any more. + * + * Since vop version(3,4), vop timing is frame effect, not need config + * timing register on vblank. */ - if (clk_get_rate(vop->dclk)) { + if (clk_get_rate(vop->dclk) && + !(VOP_MAJOR(version) == 3 && VOP_MINOR(version) >= 4)) { /* * Rk3288 vop timing register is immediately, when configure * display timing on display time, may cause tearing. -- 2.34.1