From a827ecbec6bd60eb74f3cedc9a0c3b08eaece0a5 Mon Sep 17 00:00:00 2001
From: WeiYong Bi <bivvy.bi@rock-chips.com>
Date: Wed, 21 Jun 2017 09:09:57 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3399: add dsi1 node

Change-Id: I964f047b0cf9f6355d61630d03181f229fdd8c15
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 49 +++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 163861efd3a1..4048b226deef 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -74,6 +74,8 @@
 		serial2 = &uart2;
 		serial3 = &uart3;
 		serial4 = &uart4;
+		dsi0 = &dsi;
+		dsi1 = &dsi1;
 	};
 
 	cpus {
@@ -1753,6 +1755,11 @@
 				reg = <3>;
 				remote-endpoint = <&dp_in_vopl>;
 			};
+
+			vopl_out_dsi1: endpoint@4 {
+				reg = <4>;
+				remote-endpoint = <&dsi1_in_vopl>;
+			};
 		};
 	};
 
@@ -1817,6 +1824,11 @@
 				reg = <3>;
 				remote-endpoint = <&dp_in_vopb>;
 			};
+
+			vopb_out_dsi1: endpoint@4 {
+				reg = <4>;
+				remote-endpoint = <&dsi1_in_vopb>;
+			};
 		};
 	};
 
@@ -1899,12 +1911,14 @@
 	};
 
 	dsi: dsi@ff960000 {
-		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+		compatible = "rockchip,rk3399-mipi-dsi";
 		reg = <0x0 0xff960000 0x0 0x8000>;
 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
 			 <&cru SCLK_DPHY_TX0_CFG>;
 		clock-names = "ref", "pclk", "phy_cfg";
+		resets = <&cru SRST_P_MIPI_DSI0>;
+		reset-names = "pclkrstz";
 		power-domains = <&power RK3399_PD_VIO>;
 		rockchip,grf = <&grf>;
 		#address-cells = <1>;
@@ -1929,6 +1943,39 @@
 		};
 	};
 
+	dsi1: dsi@ff968000 {
+		compatible = "rockchip,rk3399-mipi-dsi";
+		reg = <0x0 0xff968000 0x0 0x8000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+			 <&cru SCLK_DPHY_TX1RX1_CFG>;
+		clock-names = "ref", "pclk", "phy_cfg";
+		resets = <&cru SRST_P_MIPI_DSI1>;
+		reset-names = "pclkrstz";
+		power-domains = <&power RK3399_PD_VIO>;
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports {
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dsi1_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_dsi1>;
+				};
+
+				dsi1_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_dsi1>;
+				};
+			};
+		};
+	};
+
 	edp: edp@ff970000 {
 		compatible = "rockchip,rk3399-edp";
 		reg = <0x0 0xff970000 0x0 0x8000>;
-- 
2.34.1