From a898ce687a3a835ae47548101fe847ca17d85f48 Mon Sep 17 00:00:00 2001
From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Tue, 12 Dec 2006 17:10:13 +0000
Subject: [PATCH] more general matching of the MVN instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32484 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMISelDAGToDAG.cpp | 37 +++++++++---------------------
 lib/Target/ARM/ARMInstrInfo.td     | 11 ---------
 test/CodeGen/ARM/mvn.ll            |  8 ++++++-
 3 files changed, 18 insertions(+), 38 deletions(-)

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index a796431ae78..6abc097c4c4 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -849,13 +849,17 @@ bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand Op,
   case ISD::Constant: {
     uint32_t val = cast<ConstantSDNode>(N)->getValue();
     if(!isRotInt8Immediate(val)) {
-      if (isRotInt8Immediate(~val))
-        return false; //use MVN
-      Constant    *C = ConstantInt::get(Type::UIntTy, val);
-      int  alignment = 2;
-      SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
-      SDOperand    Z = CurDAG->getTargetConstant(0,     MVT::i32);
-      SDNode      *n = CurDAG->getTargetNode(ARM::LDR,  MVT::i32, Addr, Z);
+      SDOperand Z = CurDAG->getTargetConstant(0,     MVT::i32);
+      SDNode *n;
+      if (isRotInt8Immediate(~val)) {
+        SDOperand C = CurDAG->getTargetConstant(~val,  MVT::i32);
+        n           = CurDAG->getTargetNode(ARM::MVN,  MVT::i32, C, Z, Z);
+     } else {
+        Constant    *C = ConstantInt::get(Type::UIntTy, val);
+        int  alignment = 2;
+        SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
+        n              = CurDAG->getTargetNode(ARM::LDR,  MVT::i32, Addr, Z);
+      }
       Arg            = SDOperand(n, 0);
     } else
       Arg            = CurDAG->getTargetConstant(val,    MVT::i32);
@@ -887,25 +891,6 @@ bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand Op,
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode1a(SDOperand Op,
-				       SDOperand N,
-				       SDOperand &Arg,
-				       SDOperand &Shift,
-				       SDOperand &ShiftType) {
-  if (N.getOpcode() != ISD::Constant)
-    return false;
-
-  uint32_t val = ~cast<ConstantSDNode>(N)->getValue();
-  if(!isRotInt8Immediate(val))
-    return false;
-
-  Arg       = CurDAG->getTargetConstant(val,    MVT::i32);
-  Shift     = CurDAG->getTargetConstant(0,             MVT::i32);
-  ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
-
-  return true;
-}
-
 bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
                                       SDOperand &Arg, SDOperand &Offset) {
   //TODO: complete and cleanup!
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2d1bfc0e554..4be2b74a5eb 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -18,11 +18,6 @@ def op_addr_mode1 : Operand<iPTR> {
   let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
 }
 
-def op_addr_mode1a : Operand<iPTR> {
-  let PrintMethod = "printAddrMode1";
-  let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
-}
-
 def op_addr_mode2 : Operand<iPTR> {
   let PrintMethod = "printAddrMode2";
   let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -38,9 +33,6 @@ def op_addr_mode5 : Operand<iPTR> {
 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
                                 []>;
 
-//Addressing Mode 1a: MVN hack
-def addr_mode1a : ComplexPattern<iPTR, 3, "SelectAddrMode1a", [imm], []>;
-
 //Addressing Mode 2: Load and Store Word or Unsigned Byte
 def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
 
@@ -201,9 +193,6 @@ def MOV   : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
 def MVN     : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
                        "mvn $dst, $src", [(set IntRegs:$dst, (not addr_mode1:$src))]>;
 
-def MVN2    : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
-                       "mvn $dst, $src", [(set IntRegs:$dst, addr_mode1a:$src)]>;
-
 def ADD     : Addr1BinOp<"add",  add>;
 def ADCS    : Addr1BinOp<"adcs", adde>;
 def ADDS    : Addr1BinOp<"adds", addc>;
diff --git a/test/CodeGen/ARM/mvn.ll b/test/CodeGen/ARM/mvn.ll
index b825cf8ea9b..2a130c20404 100644
--- a/test/CodeGen/ARM/mvn.ll
+++ b/test/CodeGen/ARM/mvn.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mvn | wc -l | grep 6
+; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep mvn | wc -l | grep 7
 
 int %f1() {
 entry:
@@ -64,3 +64,9 @@ cond_true4848:          ; preds = %bb4835
         %abc = add int %tmp4851, %tmp4845
         ret int %abc
 }
+
+bool %f10(int %a) {
+entry:
+        %tmp102 = seteq int -2, %a              ; <bool> [#uses=1]
+        ret bool %tmp102
+}
-- 
2.34.1