From ab2fed6622aa220d95f2379126f1c0ba2e730b2a Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Fri, 2 May 2014 15:41:47 +0000 Subject: [PATCH] R600: Expand vector sin and cos. v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelLowering.cpp | 2 ++ test/CodeGen/R600/llvm.cos.ll | 43 ++++++++++++++++++------- test/CodeGen/R600/llvm.sin.ll | 44 +++++++++++++++++++------- 3 files changed, 67 insertions(+), 22 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 8adf7a96f0c..2c751a8be58 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -246,6 +246,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : MVT::SimpleValueType VT = FloatTypes[x]; setOperationAction(ISD::FABS, VT, Expand); setOperationAction(ISD::FADD, VT, Expand); + setOperationAction(ISD::FCOS, VT, Expand); setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FPOW, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); @@ -253,6 +254,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FMUL, VT, Expand); setOperationAction(ISD::FRINT, VT, Expand); setOperationAction(ISD::FSQRT, VT, Expand); + setOperationAction(ISD::FSIN, VT, Expand); setOperationAction(ISD::FSUB, VT, Expand); setOperationAction(ISD::SELECT, VT, Expand); } diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll index aaf2305dd0b..9e7a4deda69 100644 --- a/test/CodeGen/R600/llvm.cos.ll +++ b/test/CodeGen/R600/llvm.cos.ll @@ -1,19 +1,40 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC -;CHECK: MULADD_IEEE * -;CHECK: FRACT * -;CHECK: ADD * -;CHECK: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;FUNC-LABEL: test +;EG: MULADD_IEEE * +;EG: FRACT * +;EG: ADD * +;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG-NOT: COS +;SI: V_COS_F32 +;SI-NOT: V_COS_F32 -define void @test(<4 x float> inreg %reg0) #0 { - %r0 = extractelement <4 x float> %reg0, i32 0 - %r1 = call float @llvm.cos.f32(float %r0) - %vec = insertelement <4 x float> undef, float %r1, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) +define void @test(float addrspace(1)* %out, float %x) #1 { + %cos = call float @llvm.cos.f32(float %x) + store float %cos, float addrspace(1)* %out + ret void +} + +;FUNC-LABEL: testv +;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG-NOT: COS +;SI: V_COS_F32 +;SI: V_COS_F32 +;SI: V_COS_F32 +;SI: V_COS_F32 +;SI-NOT: V_COS_F32 + +define void @testv(<4 x float> addrspace(1)* %out, <4 x float> inreg %vx) #1 { + %cos = call <4 x float> @llvm.cos.v4f32(<4 x float> %vx) + store <4 x float> %cos, <4 x float> addrspace(1)* %out ret void } declare float @llvm.cos.f32(float) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare <4 x float> @llvm.cos.v4f32(<4 x float>) readnone attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll index 9eb998315fe..41c363cc871 100644 --- a/test/CodeGen/R600/llvm.sin.ll +++ b/test/CodeGen/R600/llvm.sin.ll @@ -1,19 +1,41 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC -;CHECK: MULADD_IEEE * -;CHECK: FRACT * -;CHECK: ADD * -;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;FUNC-LABEL: test +;EG: MULADD_IEEE * +;EG: FRACT * +;EG: ADD * +;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG-NOT: SIN +;SI: V_MUL_F32 +;SI: V_SIN_F32 +;SI-NOT: V_SIN_F32 -define void @test(<4 x float> inreg %reg0) #0 { - %r0 = extractelement <4 x float> %reg0, i32 0 - %r1 = call float @llvm.sin.f32( float %r0) - %vec = insertelement <4 x float> undef, float %r1, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) +define void @test(float addrspace(1)* %out, float %x) #1 { + %sin = call float @llvm.sin.f32(float %x) + store float %sin, float addrspace(1)* %out + ret void +} + +;FUNC-LABEL: testv +;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +;EG-NOT: SIN +;SI: V_SIN_F32 +;SI: V_SIN_F32 +;SI: V_SIN_F32 +;SI: V_SIN_F32 +;SI-NOT: V_SIN_F32 + +define void @testv(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 { + %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx) + store <4 x float> %sin, <4 x float> addrspace(1)* %out ret void } declare float @llvm.sin.f32(float) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare <4 x float> @llvm.sin.v4f32(<4 x float>) readnone attributes #0 = { "ShaderType"="0" } -- 2.34.1