From abbe0a20474740ff15e1b7cf3c46bff287b446ef Mon Sep 17 00:00:00 2001 From: zsq Date: Fri, 8 Aug 2014 16:34:09 +0800 Subject: [PATCH] fix rga/rga2 driver exist compile error /change rga/rga2 dsti name to rga_drv/rga2_drv --- arch/arm/boot/dts/rk312x.dtsi | 2 +- drivers/video/rockchip/rga/rga.h | 115 +++++++++++--------- drivers/video/rockchip/rga/rga_drv.c | 114 ++++++++++++------- drivers/video/rockchip/rga/rga_mmu_info.c | 85 ++++++++++----- drivers/video/rockchip/rga/rga_reg_info.c | 80 ++++++++------ drivers/video/rockchip/rga/rga_reg_info.h | 14 ++- drivers/video/rockchip/rga/rga_rop.h | 10 +- drivers/video/rockchip/rga2/rga2.h | 3 - drivers/video/rockchip/rga2/rga2_drv.c | 8 +- drivers/video/rockchip/rga2/rga2_reg_info.c | 4 +- drivers/video/rockchip/rga2/rga2_rop.h | 6 +- 11 files changed, 264 insertions(+), 177 deletions(-) diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index 8037e9a8a3de..ecdc3dc45908 100755 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -690,7 +690,7 @@ }; rga: rga@1010c000 { - compatible = "rockchip,rga"; + compatible = "rockchip,rga_drv"; reg = <0x1010c000 0x1000>; interrupts = ; clocks = <&clk_gates0 11>, <&clk_gates1 4>; diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h index f2972a8e2f5e..fbd36e2f1f33 100755 --- a/drivers/video/rockchip/rga/rga.h +++ b/drivers/video/rockchip/rga/rga.h @@ -2,6 +2,8 @@ #define _RGA_DRIVER_H_ #include +#include + #define RGA_BLIT_SYNC 0x5017 #define RGA_BLIT_ASYNC 0x5018 @@ -11,7 +13,7 @@ #define RGA_REG_CTRL_LEN 0x8 /* 8 */ -#define RGA_REG_CMD_LEN 0x1c /* 28 */ +#define RGA_REG_CMD_LEN 0x20 /* 32 */ #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ #define RGA_OUT_OF_RESOURCES -10 @@ -26,7 +28,7 @@ /* RGA process mode enum */ enum -{ +{ bitblt_mode = 0x0, color_palette_mode = 0x1, color_fill_mode = 0x2, @@ -55,7 +57,7 @@ enum /* RGA rotate mode */ -enum +enum { rotate_mode0 = 0x0, /* no rotate */ rotate_mode1 = 0x1, /* rotate */ @@ -74,13 +76,13 @@ enum /* -// Alpha Red Green Blue -{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 -{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 +// Alpha Red Green Blue +{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 +{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 -{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 -{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 +{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 +{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 @@ -95,39 +97,39 @@ enum RK_FORMAT_RGBA_5551 = 0x5, RK_FORMAT_RGBA_4444 = 0x6, RK_FORMAT_BGR_888 = 0x7, - - RK_FORMAT_YCbCr_422_SP = 0x8, - RK_FORMAT_YCbCr_422_P = 0x9, - RK_FORMAT_YCbCr_420_SP = 0xa, + + RK_FORMAT_YCbCr_422_SP = 0x8, + RK_FORMAT_YCbCr_422_P = 0x9, + RK_FORMAT_YCbCr_420_SP = 0xa, RK_FORMAT_YCbCr_420_P = 0xb, - RK_FORMAT_YCrCb_422_SP = 0xc, - RK_FORMAT_YCrCb_422_P = 0xd, - RK_FORMAT_YCrCb_420_SP = 0xe, + RK_FORMAT_YCrCb_422_SP = 0xc, + RK_FORMAT_YCrCb_422_P = 0xd, + RK_FORMAT_YCrCb_420_SP = 0xe, RK_FORMAT_YCrCb_420_P = 0xf, - + RK_FORMAT_BPP1 = 0x10, RK_FORMAT_BPP2 = 0x11, RK_FORMAT_BPP4 = 0x12, RK_FORMAT_BPP8 = 0x13, }; - - + + typedef struct rga_img_info_t { unsigned int yrgb_addr; /* yrgb mem addr */ unsigned int uv_addr; /* cb/cr mem addr */ unsigned int v_addr; /* cr mem addr */ unsigned int format; //definition by RK_FORMAT - + unsigned short act_w; unsigned short act_h; unsigned short x_offset; unsigned short y_offset; - + unsigned short vir_w; unsigned short vir_h; - + unsigned short endian_mode; //for BPP unsigned short alpha_swap; } @@ -163,8 +165,8 @@ typedef struct RECT { unsigned short xmin; unsigned short xmax; // width - 1 - unsigned short ymin; - unsigned short ymax; // height - 1 + unsigned short ymin; + unsigned short ymax; // height - 1 } RECT; typedef struct RGB @@ -225,23 +227,23 @@ line_draw_t; struct rga_req { uint8_t render_mode; /* (enum) process mode sel */ - + rga_img_info_t src; /* src image info */ rga_img_info_t dst; /* dst image info */ rga_img_info_t pat; /* patten image info */ uint32_t rop_mask_addr; /* rop4 mask addr */ uint32_t LUT_addr; /* LUT addr */ - + RECT clip; /* dst clip window default value is dst_vir */ /* value from [0, w-1] / [0, h-1]*/ - + int32_t sina; /* dst angle default value 0 16.16 scan from table */ - int32_t cosa; /* dst angle default value 0 16.16 scan from table */ + int32_t cosa; /* dst angle default value 0 16.16 scan from table */ uint16_t alpha_rop_flag; /* alpha rop process flag */ /* ([0] = 1 alpha_rop_enable) */ - /* ([1] = 1 rop enable) */ + /* ([1] = 1 rop enable) */ /* ([2] = 1 fading_enable) */ /* ([3] = 1 PD_enable) */ /* ([4] = 1 alpha cal_mode_sel) */ @@ -249,32 +251,32 @@ struct rga_req { /* ([6] = 1 gradient fill mode sel) */ /* ([7] = 1 AA_enable) */ - uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ - + uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ + uint32_t color_key_max; /* color key max */ - uint32_t color_key_min; /* color key min */ + uint32_t color_key_min; /* color key min */ uint32_t fg_color; /* foreground color */ uint32_t bg_color; /* background color */ COLOR_FILL gr_color; /* color fill use gradient */ - + line_draw_t line_draw_info; - + FADING fading; - + uint8_t PD_mode; /* porter duff alpha mode sel */ - + uint8_t alpha_global_value; /* global alpha value */ - + uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ - + uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ - + uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ - uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ - + uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ + uint8_t endian_mode; /* 0/big endian 1/little endian*/ uint8_t rotate_mode; /* (enum) rotate mode */ @@ -284,7 +286,7 @@ struct rga_req { /* 0x3, y_mirror */ uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ - + MMU mmu_info; /* mmu information */ uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ @@ -292,14 +294,17 @@ struct rga_req { /* ([4] zero mode en) */ /* ([5] dst alpha mode) */ - uint8_t src_trans_mode; + uint8_t src_trans_mode; + + struct sg_table *sg_src; + struct sg_table *sg_dst; }; - + typedef struct TILE_INFO { int64_t matrix[4]; - + uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */ uint16_t tile_y_num; /* y axis tile num */ @@ -323,9 +328,9 @@ typedef struct TILE_INFO int32_t y_dy; mdp_img_act dst_ctrl; - + } -TILE_INFO; +TILE_INFO; /** @@ -348,15 +353,15 @@ typedef struct rga_session { atomic_t num_done; } rga_session; -struct rga_reg { +struct rga_reg { rga_session *session; struct list_head session_link; /* link to rga service session */ struct list_head status_link; /* link to register set list */ uint32_t sys_reg[RGA_REG_CTRL_LEN]; uint32_t cmd_reg[RGA_REG_CMD_LEN]; - + uint32_t *MMU_base; - //atomic_t int_enable; + //atomic_t int_enable; //struct rga_req req; }; @@ -371,9 +376,9 @@ typedef struct rga_service_info { struct list_head done; /* link to link_reg in struct vpu_reg */ struct list_head session; /* link to list_session in struct vpu_session */ atomic_t total_running; - + struct rga_reg *reg; - + uint32_t cmd_buff[28*8];/* cmd_buff for rga */ uint32_t *pre_scale_buf; atomic_t int_disable; /* 0 int enable 1 int disable */ @@ -390,7 +395,7 @@ typedef struct rga_service_info { -#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) +#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x) #define RGA_BASE 0x1010c000 #elif defined(CONFIG_ARCH_RK30) #define RGA_BASE 0x10114000 @@ -444,7 +449,7 @@ typedef struct rga_service_info { #define RGA_DST_VIR_INFO 0x150 #define RGA_DST_CTR_INFO 0x154 -#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat +#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat //Alpha/ROP Registers #define RGA_ALPHA_CON 0x158 @@ -466,10 +471,12 @@ typedef struct rga_service_info { #define RGA_MMU_TBL 0x16c //repeat +#define RGA_YUV_OUT_CFG 0x170 +#define RGA_DST_UV_MST 0x174 + #define RGA_BLIT_COMPLETE_EVENT 1 long rga_ioctl_kernel(struct rga_req *req); - #endif /*_RK29_IPP_DRIVER_H_*/ diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c index e34920832d19..59b571eaacac 100755 --- a/drivers/video/rockchip/rga/rga_drv.c +++ b/drivers/video/rockchip/rga/rga_drv.c @@ -84,6 +84,9 @@ ktime_t rga_end; rga_session rga_session_global; +long (*rga_ioctl_kernel_p)(struct rga_req *); + + struct rga_drvdata { struct miscdevice miscdev; struct device dev; @@ -139,8 +142,8 @@ static void print_info(struct rga_req *req) req->src.act_w, req->src.act_h, req->src.vir_w, req->src.vir_h); printk("src : x_off = %.8x y_off = %.8x\n", req->src.x_offset, req->src.y_offset); - printk("dst : yrgb_addr = %.8x, dst.uv_addr = %.8x, dst.v_addr = %.8x\n", - req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr); + printk("dst : yrgb_addr = %.8x, dst.uv_addr = %.8x, dst.v_addr = %.8x, format = %d\n", + req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, req->dst.format); printk("dst : x_off = %.8x y_off = %.8x\n", req->dst.x_offset, req->dst.y_offset); printk("dst : act_w = %d, act_h = %d, vir_w = %d, vir_h = %d\n", req->dst.act_w, req->dst.act_h, req->dst.vir_w, req->dst.vir_h); @@ -439,10 +442,10 @@ static void rga_copy_reg(struct rga_reg *reg, uint32_t offset) atomic_add(1, &rga_service.cmd_num); atomic_add(1, ®->session->task_running); - cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*28; + cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*32; reg_p = (uint32_t *)reg->cmd_reg; - for(i=0; i<28; i++) + for(i=0; i<32; i++) { cmd_buf[i] = reg_p[i]; } @@ -647,6 +650,7 @@ static void rga_try_set_reg(void) printk("CMD_REG\n"); for (i=0; i<7; i++) printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]); + printk("%.8x %.8x\n", p[0 + i*4], p[1+i*4]); } #endif @@ -671,6 +675,7 @@ static void rga_try_set_reg(void) for (i=0; i<7; i++) printk("%.8x %.8x %.8x %.8x\n", rga_read(0x100 + i*16 + 0), rga_read(0x100 + i*16 + 4), rga_read(0x100 + i*16 + 8), rga_read(0x100 + i*16 + 12)); + printk("%.8x %.8x\n", rga_read(0x100 + i*16 + 0), rga_read(0x100 + i*16 + 4)); } #endif } @@ -790,40 +795,74 @@ static void rga_mem_addr_sel(struct rga_req *req) } - static int rga_convert_dma_buf(struct rga_req *req) { struct ion_handle *hdl; ion_phys_addr_t phy_addr; size_t len; + int ret; + + req->sg_src = NULL; + req->sg_dst = NULL; if(req->src.yrgb_addr) { hdl = ion_import_dma_buf(drvdata->ion_client, req->src.yrgb_addr); - ion_phys(drvdata->ion_client, hdl, &phy_addr, &len); - req->src.yrgb_addr = phy_addr; - req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h); + if (IS_ERR(hdl)) { + ret = PTR_ERR(hdl); + printk("RGA2 ERROR ion buf handle\n"); + return ret; + } + if ((req->mmu_info.mmu_flag >> 8) & 1) { + req->sg_src = ion_sg_table(drvdata->ion_client, hdl); + req->src.yrgb_addr = req->src.uv_addr; + req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h); + req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4; + } + else { + ion_phys(drvdata->ion_client, hdl, &phy_addr, &len); + req->src.yrgb_addr = phy_addr; + req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h); + req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4; + } ion_free(drvdata->ion_client, hdl); } else { req->src.yrgb_addr = req->src.uv_addr; req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h); + req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4; } if(req->dst.yrgb_addr) { hdl = ion_import_dma_buf(drvdata->ion_client, req->dst.yrgb_addr); - ion_phys(drvdata->ion_client, hdl, &phy_addr, &len); - req->dst.yrgb_addr = phy_addr; - req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h); + if (IS_ERR(hdl)) { + ret = PTR_ERR(hdl); + printk("RGA2 ERROR ion buf handle\n"); + return ret; + } + if ((req->mmu_info.mmu_flag >> 10) & 1) { + req->sg_dst = ion_sg_table(drvdata->ion_client, hdl); + req->dst.yrgb_addr = req->dst.uv_addr; + req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h); + req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4; + } + else { + ion_phys(drvdata->ion_client, hdl, &phy_addr, &len); + req->dst.yrgb_addr = phy_addr; + req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h); + req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4; + } ion_free(drvdata->ion_client, hdl); } else { req->dst.yrgb_addr = req->dst.uv_addr; - req->dst.uv_addr = req->dst.yrgb_addr + (req->src.vir_w * req->src.vir_h); + req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h); + req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4; } return 0; } + static int rga_blit(rga_session *session, struct rga_req *req) { int ret = -1; @@ -838,15 +877,15 @@ static int rga_blit(rga_session *session, struct rga_req *req) daw = req->dst.act_w; dah = req->dst.act_h; + #if RGA_TEST + print_info(req); + #endif + if(rga_convert_dma_buf(req)) { printk("RGA : DMA buf copy error\n"); return -EFAULT; } - #if RGA_TEST - print_info(req); - #endif - do { if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) { /* generate 2 cmd for pre scale */ @@ -1032,6 +1071,20 @@ static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg) long rga_ioctl_kernel(struct rga_req *req) +{ + int ret = 0; + if (!rga_ioctl_kernel_p) { + printk("rga_ioctl_kernel_p is NULL\n"); + return -1; + } + else { + ret = (*rga_ioctl_kernel_p)(req); + return ret; + } +} + + +long rga_ioctl_kernel_imp(struct rga_req *req) { int ret = 0; rga_session *session; @@ -1046,24 +1099,7 @@ long rga_ioctl_kernel(struct rga_req *req) return -EINVAL; } - switch (RGA_BLIT_SYNC) { - case RGA_BLIT_SYNC: - ret = rga_blit_sync(session, req); - break; - case RGA_BLIT_ASYNC: - break; - case RGA_FLUSH: - break; - case RGA_GET_RESULT: - break; - case RGA_GET_VERSION: - //ret = 0; - break; - default: - ERR("unknown ioctl cmd!\n"); - ret = -EINVAL; - break; - } + ret = rga_blit_sync(session, req); mutex_unlock(&rga_service.mutex); @@ -1162,7 +1198,7 @@ static struct miscdevice rga_dev ={ #if defined(CONFIG_OF) static const struct of_device_id rockchip_rga_dt_ids[] = { - { .compatible = "rockchip,rga", }, + { .compatible = "rockchip,rga_drv", }, {}, }; #endif @@ -1181,6 +1217,8 @@ static int rga_drv_probe(struct platform_device *pdev) rga_service.last_prc_src_format = 1; /* default is yuv first*/ rga_service.enable = false; + rga_ioctl_kernel_p = rga_ioctl_kernel_imp; + data = devm_kzalloc(&pdev->dev, sizeof(struct rga_drvdata), GFP_KERNEL); if(! data) { ERR("failed to allocate driver data.\n"); @@ -1303,8 +1341,8 @@ static int __init rga_init(void) return -1; } - /* malloc 8 M buf */ - for(i=0; i<2048; i++) + /* malloc 4 M buf */ + for(i=0; i<1024; i++) { buf_p = (uint32_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO); if(buf_p == NULL) @@ -1360,7 +1398,7 @@ static void __exit rga_exit(void) rga_power_off(); - for(i=0; i<2048; i++) + for(i=0; i<1024; i++) { if((uint32_t *)rga_service.pre_scale_buf[i] != NULL) { diff --git a/drivers/video/rockchip/rga/rga_mmu_info.c b/drivers/video/rockchip/rga/rga_mmu_info.c index 86e8205fbb83..a0152787a03c 100755 --- a/drivers/video/rockchip/rga/rga_mmu_info.c +++ b/drivers/video/rockchip/rga/rga_mmu_info.c @@ -397,6 +397,37 @@ static int rga_MapUserMemory(struct page **pages, return status; } +static int rga_MapION(struct sg_table *sg, + uint32_t *Memory, + int32_t pageCount) +{ + uint32_t i; + uint32_t status; + uint32_t Address; + uint32_t mapped_size = 0; + uint32_t len; + struct scatterlist *sgl = sg->sgl; + uint32_t sg_num = 0; + + status = 0; + Address = 0; + do { + len = sg_dma_len(sgl) >> PAGE_SHIFT; + Address = sg_phys(sgl); + + for(i=0; inents)); + + return 0; +} + + static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) { int SrcMemSize, DstMemSize; @@ -412,9 +443,13 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) MMU_Base = NULL; + SrcMemSize = 0; + DstMemSize = 0; + do { /* cal src buf mmu info */ + SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr, req->src.format, req->src.vir_w, req->src.act_h + req->src.y_offset, &SrcStart); @@ -422,7 +457,9 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) return -EINVAL; } + /* cal dst buf mmu info */ + DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr, req->dst.format, req->dst.vir_w, req->dst.vir_h, &DstStart); @@ -430,6 +467,7 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) return -EINVAL; } + /* Cal out the needed mem size */ AllSize = SrcMemSize + DstMemSize; @@ -447,13 +485,18 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) break; } - if(req->src.yrgb_addr < KERNEL_SPACE_VALID) + if((req->mmu_info.mmu_flag >> 8) & 1) { - ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize); - if (ret < 0) { - pr_err("rga map src memory failed\n"); - status = ret; - break; + if (req->sg_src) { + ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize); + } + else { + ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize); + if (ret < 0) { + pr_err("rga map src memory failed\n"); + status = ret; + break; + } } } else @@ -466,46 +509,28 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req) /* MMU table copy from pre scale table */ for(i=0; idst.yrgb_addr < KERNEL_SPACE_VALID) - { - #if 0 - ktime_t start, end; - start = ktime_get(); - #endif + if ((req->mmu_info.mmu_flag >> 10) & 1) { ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize); if (ret < 0) { pr_err("rga map dst memory failed\n"); status = ret; break; } - - #if 0 - end = ktime_get(); - end = ktime_sub(end, start); - printk("dst mmu map time = %d\n", (int)ktime_to_us(end)); - #endif } - else - { + else { MMU_p = MMU_Base + SrcMemSize; for(i=0; idst.format); @@ -696,39 +701,46 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg) *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw); - if (msg->render_mode == pre_scaling_mode) + *bRGA_DST_UV_MST = 0; + *bRGA_YUV_OUT_CFG = 0; + switch(msg->dst.format) { - switch(msg->dst.format) - { - case RK_FORMAT_YCbCr_422_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCbCr_422_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCbCr_420_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCbCr_420_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCrCb_422_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCrCb_422_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); - break; - case RK_FORMAT_YCrCb_420_SP : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); - break; - case RK_FORMAT_YCrCb_420_P : - *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); - break; - } + case RK_FORMAT_YCbCr_422_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (1 << 3) | 1 | ((msg->yuv2rgb_mode >> 4) & 2); + break; + case RK_FORMAT_YCbCr_422_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCbCr_420_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (1 << 3)|(1 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2); + break; + case RK_FORMAT_YCbCr_420_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCrCb_422_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (0 << 3)|(0 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2); + break; + case RK_FORMAT_YCrCb_422_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw); + break; + case RK_FORMAT_YCrCb_420_SP : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw); + *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off)); + *bRGA_YUV_OUT_CFG |= (0 << 3)|(1 << 1) | 1 | ((msg->yuv2rgb_mode >> 4) & 2); + break; + case RK_FORMAT_YCrCb_420_P : + *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw); + break; } rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21 @@ -750,6 +762,10 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg) *bRGA_DST_VIR_INFO = reg; *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16); + if (msg->render_mode == pre_scaling_mode) { + *bRGA_YUV_OUT_CFG &= 0xfffffffe; + } + return 0; } diff --git a/drivers/video/rockchip/rga/rga_reg_info.h b/drivers/video/rockchip/rga/rga_reg_info.h index a7ca510a3d92..e3d7dc0ba016 100755 --- a/drivers/video/rockchip/rga/rga_reg_info.h +++ b/drivers/video/rockchip/rga/rga_reg_info.h @@ -73,7 +73,7 @@ #define rRGA_DST_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO)) #define rRGA_DST_CTR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO)) -#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat +#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat //Alpha/ROP Registers #define rRGA_ALPHA_CON (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON)) @@ -258,7 +258,7 @@ #define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30) #define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31) - + /* RGA_ALPHA_CON */ #define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 ) #define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 ) @@ -360,7 +360,7 @@ #define RGA_DST_VIR_INFO_OFFSET 0x50 #define RGA_DST_CTR_INFO_OFFSET 0x54 -#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat +#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat #define RGA_ALPHA_CON_OFFSET 0x58 #define RGA_FADING_CON_OFFSET 0x5c @@ -435,7 +435,7 @@ #define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100) #define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100) -#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat +#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat #define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100) @@ -451,7 +451,11 @@ #define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat #define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100) -#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100) +#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100) + +#define RGA_YUV_OUT_CFG_OFFSET (RGA_YUV_OUT_CFG-0x100) +#define RGA_DST_UV_MST_OFFSET (RGA_DST_UV_MST-0x100) + void matrix_cal(const struct rga_req *msg, TILE_INFO *tile); diff --git a/drivers/video/rockchip/rga/rga_rop.h b/drivers/video/rockchip/rga/rga_rop.h index c4be6352cc0f..685818fc9e68 100755 --- a/drivers/video/rockchip/rga/rga_rop.h +++ b/drivers/video/rockchip/rga/rga_rop.h @@ -1,14 +1,12 @@ #ifndef __RGA_ROP_H__ #define __RGA_ROP_H__ -#include "rga_type.h" - -UWORD32 ROP3_code[256] = +unsigned int ROP3_code[256] = { 0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0 0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005, - 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1 + 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1 0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0, 0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2 @@ -28,8 +26,8 @@ UWORD32 ROP3_code[256] = 0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062, 0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7 - - 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0, + + 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0, 0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8 0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051, diff --git a/drivers/video/rockchip/rga2/rga2.h b/drivers/video/rockchip/rga2/rga2.h index d67cba9ef9dc..ba2c1ddfa225 100644 --- a/drivers/video/rockchip/rga2/rga2.h +++ b/drivers/video/rockchip/rga2/rga2.h @@ -631,7 +631,4 @@ struct rga2_service_info { #define RGA2_MODE_CTRL 0x100 #define RGA_BLIT_COMPLETE_EVENT 1 -long rga_ioctl_kernel(struct rga_req *req); - - #endif /*_RK29_IPP_DRIVER_H_*/ diff --git a/drivers/video/rockchip/rga2/rga2_drv.c b/drivers/video/rockchip/rga2/rga2_drv.c index baafc54521e7..5f908f422c85 100755 --- a/drivers/video/rockchip/rga2/rga2_drv.c +++ b/drivers/video/rockchip/rga2/rga2_drv.c @@ -79,6 +79,8 @@ ktime_t rga2_end; int rga2_flag = 0; +extern long (*rga_ioctl_kernel_p)(struct rga_req *); + rga2_session rga2_session_global; struct rga2_drvdata_t { @@ -1109,7 +1111,7 @@ static struct miscdevice rga2_dev ={ }; static const struct of_device_id rockchip_rga_dt_ids[] = { - { .compatible = "rockchip,rga2", }, + { .compatible = "rockchip,rga2_drv", }, {}, }; @@ -1126,6 +1128,8 @@ static int rga2_drv_probe(struct platform_device *pdev) rga2_service.last_prc_src_format = 1; /* default is yuv first*/ rga2_service.enable = false; + rga_ioctl_kernel_p = rga2_ioctl_kernel; + data = devm_kzalloc(&pdev->dev, sizeof(struct rga2_drvdata_t), GFP_KERNEL); if(NULL == data) { @@ -1226,7 +1230,7 @@ static struct platform_driver rga2_driver = { .remove = rga2_drv_remove, .driver = { .owner = THIS_MODULE, - .name = "rga", + .name = "rga2", .of_match_table = of_match_ptr(rockchip_rga_dt_ids), }, }; diff --git a/drivers/video/rockchip/rga2/rga2_reg_info.c b/drivers/video/rockchip/rga2/rga2_reg_info.c index a01dc32e2e3b..82c34e9c1c23 100644 --- a/drivers/video/rockchip/rga2/rga2_reg_info.c +++ b/drivers/video/rockchip/rga2/rga2_reg_info.c @@ -30,9 +30,11 @@ #include #include "rga2_reg_info.h" -#include "rga2_rop.h" +#include "../rga/rga_type.h" +//#include "../rga/rga_rop.h" #include "rga2.h" +extern unsigned int ROP3_code[256]; void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg) diff --git a/drivers/video/rockchip/rga2/rga2_rop.h b/drivers/video/rockchip/rga2/rga2_rop.h index d859543d6a45..60d90b8304de 100644 --- a/drivers/video/rockchip/rga2/rga2_rop.h +++ b/drivers/video/rockchip/rga2/rga2_rop.h @@ -3,10 +3,7 @@ #include "rga2_type.h" -extern UWORD32 ROP3_code[256]; - -#if 0 -extern UWORD32 ROP3_code[256] = +UWORD32 ROP3_code[256] = { 0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0 0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005, @@ -56,6 +53,5 @@ extern UWORD32 ROP3_code[256] = 0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870, 0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f }; -#endif #endif -- 2.34.1