From ac75497ee3371c50ef9c064ec9d626717af780dd Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Thu, 24 Mar 2016 16:01:36 +0800 Subject: [PATCH] clk: rockchip: rk3399: fix PPLL is redefined and ID shouldn't be 0 PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0. Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c Signed-off-by: Xing Zheng --- include/dt-bindings/clock/rk3399-cru.h | 28 ++++++++++++++------------ 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 0715e66db20a..51122c0146c1 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -24,9 +24,8 @@ #define PLL_GPLL 5 #define PLL_NPLL 6 #define PLL_VPLL 7 -#define PLL_PPLL 8 -#define ARMCLKL 9 -#define ARMCLKB 10 +#define ARMCLKL 8 +#define ARMCLKB 9 /* sclk gates (special clocks) */ #define SCLK_I2C1 65 @@ -337,16 +336,19 @@ #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1) /* pmu-clocks indices */ -#define SCLK_32K_SUSPEND_PMU 0 -#define SCLK_SPI3_PMU 1 -#define SCLK_TIMER12_PMU 2 -#define SCLK_TIMER13_PMU 3 -#define SCLK_UART4_PMU 4 -#define SCLK_PVTM_PMU 5 -#define SCLK_WIFI_PMU 6 -#define SCLK_I2C0_PMU 7 -#define SCLK_I2C4_PMU 8 -#define SCLK_I2C8_PMU 9 + +#define PLL_PPLL 1 + +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 #define PCLK_SRC_PMU 19 #define PCLK_PMU 20 -- 2.34.1