From aca09a9d4b265f7d12d1776691773507e12a1515 Mon Sep 17 00:00:00 2001 From: Charlie Turner Date: Tue, 27 Oct 2015 10:25:20 +0000 Subject: [PATCH] [ARM] Expand ROTL and ROTR of vector value types Summary: After D13851 landed, we saw backend crashes when compiling the reduced test case included in this patch. The right fix seems to be to allow these vector types for expansion in instruction selection. Reviewers: rengolin, t.p.northover Subscribers: RKSimon, t.p.northover, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251401 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 4 ++++ lib/Target/ARM/ARMISelLowering.cpp | 6 +++++- test/CodeGen/AArch64/rotate.ll | 14 ++++++++++++++ test/CodeGen/ARM/rotate.ll | 14 ++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/AArch64/rotate.ll create mode 100644 test/CodeGen/ARM/rotate.ll diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index fd33f879d4c..428624cd894 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -220,6 +220,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, // AArch64 lacks both left-rotate and popcount instructions. setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::ROTL, MVT::i64, Expand); + for (MVT VT : MVT::vector_valuetypes()) { + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + } // AArch64 doesn't have {U|S}MUL_LOHI. setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 49f8918b8dd..91edc12dc11 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -718,7 +718,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, } // ARM does not have ROTL. - setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + for (MVT VT : MVT::vector_valuetypes()) { + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + } setOperationAction(ISD::CTTZ, MVT::i32, Custom); setOperationAction(ISD::CTPOP, MVT::i32, Expand); if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) diff --git a/test/CodeGen/AArch64/rotate.ll b/test/CodeGen/AArch64/rotate.ll new file mode 100644 index 00000000000..5ac86d5f59c --- /dev/null +++ b/test/CodeGen/AArch64/rotate.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=aarch64--linux-gnueabihf | FileCheck %s + +;; This used to cause a backend crash about not being able to +;; select ROTL. Make sure if generates the basic ushr/shl. +define <2 x i64> @testcase(<2 x i64>* %in) { +; CHECK-LABEL: testcase +; CHECK: ushr {{v[0-9]+}}.2d +; CHECK: shl {{v[0-9]+}}.2d + %1 = load <2 x i64>, <2 x i64>* %in + %2 = lshr <2 x i64> %1, + %3 = shl <2 x i64> %1, + %4 = or <2 x i64> %2, %3 + ret <2 x i64> %4 +} diff --git a/test/CodeGen/ARM/rotate.ll b/test/CodeGen/ARM/rotate.ll new file mode 100644 index 00000000000..f3f7de2160f --- /dev/null +++ b/test/CodeGen/ARM/rotate.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s + +;; This used to cause a backend crash about not being able to +;; select ROTL. Make sure if generates the basic VSHL/VSHR. +define <2 x i64> @testcase(<2 x i64>* %in) { +; CHECK-LABEL: testcase +; CHECK: vshl.i64 +; CHECK: vshr.u64 + %1 = load <2 x i64>, <2 x i64>* %in + %2 = lshr <2 x i64> %1, + %3 = shl <2 x i64> %1, + %4 = or <2 x i64> %2, %3 + ret <2 x i64> %4 +} -- 2.34.1