From ad51d8c8bb764d307b7693d6d31258ffeff4e4ef Mon Sep 17 00:00:00 2001 From: "lw@rock-chips.com" Date: Sun, 5 Aug 2012 13:02:32 +0800 Subject: [PATCH] phonepad:modify tps65910_pre_init to fix rtc bug --- arch/arm/mach-rk30/board-rk30-sdk-tps65910.c | 163 ++++++++++--------- arch/arm/mach-rk30/include/mach/gpio.h | 2 +- drivers/mfd/tps65910.c | 11 +- include/linux/mfd/tps65910.h | 156 +----------------- 4 files changed, 95 insertions(+), 237 deletions(-) diff --git a/arch/arm/mach-rk30/board-rk30-sdk-tps65910.c b/arch/arm/mach-rk30/board-rk30-sdk-tps65910.c index b6d4c27d246b..906c04928d3a 100755 --- a/arch/arm/mach-rk30/board-rk30-sdk-tps65910.c +++ b/arch/arm/mach-rk30/board-rk30-sdk-tps65910.c @@ -39,100 +39,99 @@ int tps65910_pre_init(struct tps65910 *tps65910){ //gpio_request(PMU_POWER_SLEEP, "NULL"); //gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH); - val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL2); + val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DEVCTRL2 reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n"); return val; } /* Set sleep state active high and allow device turn-off after PWRON long press */ - val |= (TPS65910_DEV2_SLEEPSIG_POL | TPS65910_DEV2_PWON_LP_OFF); + val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK); - err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL2, val); + err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL2 reg\n"); + printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n"); return err; } #if 1 /* set PSKIP=0 */ - val = tps65910_reg_read(tps65910, TPS65910_REG_DCDCCTRL); + val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } - //val &= ~(1 << 4); - val &= 0xFC; - // val |= 0x03; - err = tps65910_reg_write(tps65910, TPS65910_REG_DCDCCTRL, val); + val &= ~DEVCTRL_DEV_OFF_MASK; + val &= ~DEVCTRL_DEV_SLP_MASK; + err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n"); return err; } #endif /* Set the maxinum load current */ /* VDD1 */ - val = tps65910_reg_read(tps65910, TPS65910_REG_VDD1); + val = tps65910_reg_read(tps65910, TPS65910_VDD1); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_VDD1 reg\n"); + printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n"); return val; } - val |= (1<<5); - val |= (0x07<<2); - err = tps65910_reg_write(tps65910, TPS65910_REG_VDD1, val); + val |= (1<<5); //when 1: 1.5 A + val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/¦Ìs(sampling 3 Mhz/5) + err = tps65910_reg_write(tps65910, TPS65910_VDD1, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_VDD1 reg\n"); + printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n"); return err; } /* VDD2 */ - val = tps65910_reg_read(tps65910, TPS65910_REG_VDD2); + val = tps65910_reg_read(tps65910, TPS65910_VDD2); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_VDD2 reg\n"); + printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n"); return val; } - val |= (1<<5); - err = tps65910_reg_write(tps65910, TPS65910_REG_VDD2, val); + val |= (1<<5); //when 1: 1.5 A + err = tps65910_reg_write(tps65910, TPS65910_VDD2, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_VDD2 reg\n"); + printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n"); return err; } /* VIO */ - val = tps65910_reg_read(tps65910, TPS65910_REG_VIO); + val = tps65910_reg_read(tps65910, TPS65910_VIO); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_VIO reg\n"); + printk(KERN_ERR "Unable to read TPS65910_VIO reg\n"); return -EIO; } - val |= (1<<6); - err = tps65910_reg_write(tps65910, TPS65910_REG_VIO, val); + val |= (1<<6); //when 01: 1.0 A + err = tps65910_reg_write(tps65910, TPS65910_VIO, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_VIO reg\n"); + printk(KERN_ERR "Unable to write TPS65910_VIO reg\n"); return err; } #if 1 /* Mask ALL interrupts */ - err = tps65910_reg_write(tps65910,TPS65910_REG_INT_MSK, 0xFF); + err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK reg\n"); + printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n"); return err; } - err = tps65910_reg_write(tps65910, TPS65910_REG_INT_MSK2, 0x03); + err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK2 reg\n"); + printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n"); return err; } /* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */ #if 1 val = 0; - val |= (TPS65910_SR_CTL_I2C_SEL); - err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val); + val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK); + err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val); if (err) { - printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL reg\n"); + printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n"); return err; } printk(KERN_INFO "TPS65910 Set default voltage.\n"); @@ -141,9 +140,9 @@ int tps65910_pre_init(struct tps65910 *tps65910){ //read sleep control register for debug for(i=0; i<6; i++) { - err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i); + err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i); if (err) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return -EIO; } else @@ -154,65 +153,72 @@ int tps65910_pre_init(struct tps65910 *tps65910){ #if 1 //sleep control register /*set func when in sleep mode */ - val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL); + val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } - val |= (1 << 1); - err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val); - if (err) { - printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ - \n", TPS65910_REG_VDIG1); - return err; - } - /* open ldo when in sleep mode */ - val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON); + + val |= (1 << 1); + err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val); + if (err) { + printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ + \n", TPS65910_VDIG1); + return err; + } + + /* open ldo when in sleep mode */ + val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } - val &= 0; - err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON, val); - if (err) { - printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ - \n", TPS65910_REG_VDIG1); - return err; - } - /*set dc mode when in sleep mode */ - val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON); + + val &= 0; + err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val); + if (err) { + printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ + \n", TPS65910_VDIG1); + return err; + } + + /*set dc mode when in sleep mode */ + val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } - val |= 0xff; - err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON, val); - if (err) { - printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ - \n", TPS65910_REG_VDIG1); - return err; - } - /*close ldo when in sleep mode */ - val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF); + + val |= 0xff; + err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val); + if (err) { + printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ + \n", TPS65910_VDIG1); + return err; + } + + /*close ldo when in sleep mode */ + val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF); if (val<0) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return val; } - val |= 0x9B; - err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF, val); - if (err) { - printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ - \n", TPS65910_REG_VDIG1); - return err; - } + + val |= 0x9B; + err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val); + if (err) { + printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ + \n", TPS65910_VDIG1); + return err; + } #endif #if 0 //read sleep control register for debug for(i=0; i<6; i++) { - err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i); + err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i); if (err) { - printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); + printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n"); return -EIO; } else @@ -620,6 +626,7 @@ static struct tps65910_board tps65910_data = { .tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4, .tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5, .tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6, + }; diff --git a/arch/arm/mach-rk30/include/mach/gpio.h b/arch/arm/mach-rk30/include/mach/gpio.h index 24660c3713cd..e2cc0ffc0fb8 100755 --- a/arch/arm/mach-rk30/include/mach/gpio.h +++ b/arch/arm/mach-rk30/include/mach/gpio.h @@ -69,7 +69,7 @@ //¶¨ÒåGPIOµÄPIN¿Ú×î´óÊýÄ¿¡£CONFIG_SPI_FPGA_GPIO_NUM±íʾFPGAµÄPIN½ÅÊý¡£ -#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM) +#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM+CONFIG_GPIO_TPS65910_NUM) #define INVALID_GPIO -1 diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c index 42f1bd58afd6..6b16534548ad 100755 --- a/drivers/mfd/tps65910.c +++ b/drivers/mfd/tps65910.c @@ -239,7 +239,7 @@ static int tps65910_i2c_probe(struct i2c_client *i2c, struct tps65910_board *pmic_plat_data; struct tps65910_platform_data *init_data; int ret = 0; - + pmic_plat_data = dev_get_platdata(&i2c->dev); if (!pmic_plat_data) return -EINVAL; @@ -292,6 +292,7 @@ static int tps65910_i2c_probe(struct i2c_client *i2c, goto err; } } + printk("%s:irq=%d,irq_base=%d,gpio_base=%d\n",__func__,init_data->irq,init_data->irq_base,pmic_plat_data->gpio_base); return ret; @@ -310,15 +311,15 @@ int tps65910_device_shutdown(void) printk("%s\n",__func__); - val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL); + val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL); if (val<0) { printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n"); return -EIO; } - val |= (1 << 3)|(1 << 0); - val &= ~(1 << 6); //keep rtc - err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val); + val |= DEVCTRL_DEV_OFF_MASK; + val &= ~DEVCTRL_CK32K_CTRL_MASK; //keep rtc + err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val); if (err) { printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \ \n", TPS65910_REG_VDIG1); diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h index 40a56631a8cd..c093c477477b 100755 --- a/include/linux/mfd/tps65910.h +++ b/include/linux/mfd/tps65910.h @@ -368,7 +368,7 @@ #define DCDCCTRL_DCDCCKSYNC_SHIFT 0 -/*Register DEVCTRL (0x80) register.RegisterDescription */ +/*Register DEVCTRL (0x3F) register.RegisterDescription */ #define DEVCTRL_RTC_PWDN_MASK 0x40 #define DEVCTRL_RTC_PWDN_SHIFT 6 #define DEVCTRL_CK32K_CTRL_MASK 0x20 @@ -385,7 +385,7 @@ #define DEVCTRL_DEV_OFF_SHIFT 0 -/*Register DEVCTRL2 (0x80) register.RegisterDescription */ +/*Register DEVCTRL2 (0x40) register.RegisterDescription */ #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 @@ -790,157 +790,7 @@ -/* - * ---------------------------------------------------------------------------- - * Registers, all 8 bits - * ---------------------------------------------------------------------------- - */ -#define TPS65910_REG_SECONDS 0x00 -#define TPS65910_REG_MINUTES 0x01 -#define TPS65910_REG_HOURS 0x02 -#define TPS65910_REG_DAYS 0x03 -#define TPS65910_REG_MONTHS 0x04 -#define TPS65910_REG_YEARS 0x05 -#define TPS65910_REG_WEEKS 0x06 -#define TPS65910_REG_ALARM_SECONDS 0x08 -#define TPS65910_REG_ALARM_MINUTES 0x09 -#define TPS65910_REG_ALARM_HOURS 0x0A -#define TPS65910_REG_ALARM_DAYS 0x0B -#define TPS65910_REG_ALARM_MONTHS 0x0C -#define TPS65910_REG_ALARM_YEARS 0x0D - -#define TPS65910_REG_RTC_CTRL 0x10 -#define TPS65910_REG_RTC_STATUS 0x11 -#define TPS65910_REG_RTC_INTERRUPTS 0x12 -#define TPS65910_REG_RTC_COMP_LSB 0x13 -#define TPS65910_REG_RTC_COMP_MSB 0x14 -#define TPS65910_REG_RTC_RES_PROG 0x15 -#define TPS65910_REG_RTC_RESET_STATUS 0x16 -#define TPS65910_REG_BCK1 0x17 -#define TPS65910_REG_BCK2 0x18 -#define TPS65910_REG_BCK3 0x19 -#define TPS65910_REG_BCK4 0x1A -#define TPS65910_REG_BCK5 0x1B -#define TPS65910_REG_PUADEN 0x1C -#define TPS65910_REG_REF 0x1D - -#define TPS65910_REG_THERM 0x38 -#define TPS65910_REG_BBCH 0x39 - -#define TPS65910_REG_DCDCCTRL 0x3E -#define TPS65910_REG_DEVCTRL 0x3F -#define TPS65910_REG_DEVCTRL2 0x40 -#define TPS65910_REG_SLEEP_KEEP_LDO_ON 0x41 -#define TPS65910_REG_SLEEP_KEEP_RES_ON 0x42 -#define TPS65910_REG_SLEEP_SET_LDO_OFF 0x43 -#define TPS65910_REG_SLEEP_SET_RES_OFF 0x44 -#define TPS65910_REG_EN1_LDO_ASS 0x45 -#define TPS65910_REG_EN1_SMPS_ASS 0x46 -#define TPS65910_REG_EN2_LDO_ASS 0x47 -#define TPS65910_REG_EN2_SMPS_ASS 0x48 -#define TPS65910_REG_EN3_LDO_ASS 0x49 -#define TPS65910_REG_SPARE 0x4A - -#define TPS65910_REG_INT_STS 0x50 -#define TPS65910_REG_INT_MSK 0x51 -#define TPS65910_REG_INT_STS2 0x52 -#define TPS65910_REG_INT_MSK2 0x53 -#define TPS65910_REG_INT_STS3 0x54 -#define TPS65910_REG_INT_MSK3 0x55 - -#define TPS65910_REG_GPIO0 0x60 - -#define TPS65910_REG_JTAGVERNUM 0x80 - -/* TPS65910 GPIO Specific flags */ -#define TPS65910_GPIO_INT_FALLING 0 -#define TPS65910_GPIO_INT_RISING 1 - -#define TPS65910_DEBOUNCE_91_5_MS 0 -#define TPS65910_DEBOUNCE_150_MS 1 - -#define TPS65910_GPIO_PUDIS (1 << 3) -#define TPS65910_GPIO_CFG_OUTPUT (1 << 2) - - - -/* TPS65910 Interrupt events */ - -/* RTC Driver */ -#define TPS65910_RTC_ALARM_IT 0x80 -#define TPS65910_RTC_PERIOD_IT 0x40 - -/*Core Driver */ -#define TPS65910_HOT_DIE_IT 0x20 -#define TPS65910_PWRHOLD_IT 0x10 -#define TPS65910_PWRON_LP_IT 0x08 -#define TPS65910_PWRON_IT 0x04 -#define TPS65910_VMBHI_IT 0x02 -#define TPS65910_VMBGCH_IT 0x01 - -/* GPIO driver */ -#define TPS65910_GPIO_F_IT 0x02 -#define TPS65910_GPIO_R_IT 0x01 - - -#define TPS65910_VRTC_OFFMASK (1<<3) - -/* Back-up battery charger control */ -#define TPS65910_BBCHEN 0x01 - -/* Back-up battery charger voltage */ -#define TPS65910_BBSEL_3P0 0x00 -#define TPS65910_BBSEL_2P52 0x02 -#define TPS65910_BBSEL_3P15 0x04 -#define TPS65910_BBSEL_VBAT 0x06 - -/* DEVCTRL_REG flags */ -#define TPS65910_RTC_PWDNN 0x40 -#define TPS65910_CK32K_CTRL 0x20 -#define TPS65910_SR_CTL_I2C_SEL 0x10 -#define TPS65910_DEV_OFF_RST 0x08 -#define TPS65910_DEV_ON 0x04 -#define TPS65910_DEV_SLP 0x02 -#define TPS65910_DEV_OFF 0x01 - -/* DEVCTRL2_REG flags */ -#define TPS65910_DEV2_TSLOT_LENGTH 0x30 -#define TPS65910_DEV2_SLEEPSIG_POL 0x08 -#define TPS65910_DEV2_PWON_LP_OFF 0x04 -#define TPS65910_DEV2_PWON_LP_RST 0x02 -#define TPS65910_DEV2_IT_POL 0x01 - -/* Number of step-down/up converters available */ -#define TPS65910_NUM_DCDC 4 - -/* Number of LDO voltage regulators available */ -#define TPS65910_NUM_LDO 9 - -/* Number of total regulators available */ -#define TPS65910_NUM_REGULATOR (TPS65910_NUM_DCDC + TPS65910_NUM_LDO) - - -/* Regulator Supply state */ -#define SUPPLY_STATE_FLAG 0x03 -/* OFF States */ -#define TPS65910_REG_OFF_00 0x00 -#define TPS65910_REG_OFF_10 0x02 -/* OHP - on High Power */ -#define TPS65910_REG_OHP 0x01 -/* OLP - on Low Power */ -#define TPS65910_REG_OLP 0x03 - -#define TPS65910_MAX_IRQS 10 -#define TPS65910_VMBDCH_IRQ 0 -#define TPS65910_VMBHI_IRQ 1 -#define TPS65910_PWRON_IRQ 2 -#define TPS65910_PWRON_LP_IRQ 3 -#define TPS65910_PWRHOLD_IRQ 4 -#define TPS65910_HOTDIE_IRQ 5 -#define TPS65910_RTC_ALARM_IRQ 6 -#define TPS65910_RTC_PERIOD_IRQ 7 -#define TPS65910_GPIO0_R_IRQ 8 -#define TPS65910_GPIO0_F_IRQ 9 + /** -- 2.34.1