From aefe14299a05621864e6372639f372173a96bf38 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Mon, 10 Jul 2006 01:41:35 +0000 Subject: [PATCH] create the raddr addressing mode that matches any register and the frame index use raddr for the ldr instruction. This removes a dummy mov from the assembly output remove SelectFrameIndex remove isLoadFromStackSlot remove isStoreToStackSlot git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29079 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMISelDAGToDAG.cpp | 21 +++++++++------------ lib/Target/ARM/ARMInstrInfo.cpp | 22 ---------------------- lib/Target/ARM/ARMInstrInfo.h | 14 -------------- lib/Target/ARM/ARMInstrInfo.td | 6 ++++-- lib/Target/ARM/ARMRegisterInfo.cpp | 2 +- 5 files changed, 14 insertions(+), 51 deletions(-) diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 413ca5959a1..33413d6c5b5 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -95,8 +95,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, // If the argument is actually used, emit a load from the right stack // slot. if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { - //hack - unsigned ArgOffset = 0; + unsigned ArgOffset = (ArgNo - num_regs) * 4; MachineFrameInfo *MFI = MF.getFrameInfo(); unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; @@ -165,6 +164,7 @@ public: void Select(SDOperand &Result, SDOperand Op); virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + bool SelectAddrReg(SDOperand N, SDOperand &Base); // Include the pieces autogenerated from the target description. #include "ARMGenDAGISel.inc" @@ -183,12 +183,13 @@ void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { ScheduleAndEmitDAG(DAG); } -static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode *N, SDOperand Op) { - int FI = cast(N)->getIndex(); - - SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); - - Result = CurDAG->SelectNodeTo(N, ARM::movri, Op.getValueType(), TFI); +bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) { + if (FrameIndexSDNode *FI = dyn_cast(N)) { + Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType()); + } + else + Base = N; + return true; //any address fits in a register } void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { @@ -198,10 +199,6 @@ void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { default: SelectCode(Result, Op); break; - - case ISD::FrameIndex: - SelectFrameIndex(CurDAG, Result, N, Op); - break; } } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 5abe8d688d6..5437c1dda10 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -41,25 +41,3 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, return true; } } - -/// isLoadFromStackSlot - If the specified machine instruction is a direct -/// load from a stack slot, return the virtual or physical register number of -/// the destination along with the FrameIndex of the loaded stack slot. If -/// not, return 0. This predicate must return 0 if the instruction has -/// any side effects other than loading from the stack slot. -unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, - int &FrameIndex) const { - assert(0 && "not implemented"); - return 0; -} - -/// isStoreToStackSlot - If the specified machine instruction is a direct -/// store to a stack slot, return the virtual or physical register number of -/// the source reg along with the FrameIndex of the loaded stack slot. If -/// not, return 0. This predicate must return 0 if the instruction has -/// any side effects other than storing to the stack slot. -unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, - int &FrameIndex) const { - assert(0 && "not implemented"); - return 0; -} diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index b203b2235f0..e75a71d0e26 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -36,20 +36,6 @@ public: /// virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const; - - /// isLoadFromStackSlot - If the specified machine instruction is a direct - /// load from a stack slot, return the virtual or physical register number of - /// the destination along with the FrameIndex of the loaded stack slot. If - /// not, return 0. This predicate must return 0 if the instruction has - /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - - /// isStoreToStackSlot - If the specified machine instruction is a direct - /// store to a stack slot, return the virtual or physical register number of - /// the source reg along with the FrameIndex of the loaded stack slot. If - /// not, return 0. This predicate must return 0 if the instruction has - /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; }; } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 6ac9b0482ad..68913de1059 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -12,7 +12,9 @@ // //===----------------------------------------------------------------------===// - +// Define ARM specific addressing mode. + //register or frame index +def raddr : ComplexPattern; //===----------------------------------------------------------------------===// // Instructions @@ -42,7 +44,7 @@ def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>; def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr), "ldr $dst, [$addr]", - [(set IntRegs:$dst, (load IntRegs:$addr))]>; + [(set IntRegs:$dst, (load raddr:$addr))]>; def str : InstARM<(ops IntRegs:$src, IntRegs:$addr), "str $src, [$addr]", diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 007b2914a13..0c269eede23 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -81,7 +81,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - assert (MI.getOpcode() == ARM::movri); + assert (MI.getOpcode() == ARM::ldr); unsigned FrameIdx = 1; -- 2.34.1