From b017600ce33f4257d39bf9f1636771e5cf0ca640 Mon Sep 17 00:00:00 2001
From: zwl <zwl@rockchips.com>
Date: Tue, 29 Jul 2014 11:30:00 +0800
Subject: [PATCH] rk312x dts: add fb/screen/lcdc/lvds dt node

---
 arch/arm/boot/dts/rk3126-fpga.dts     | 13 +++++++++++
 arch/arm/boot/dts/rk3126-sdk.dts      | 22 ++++++++++++++++++
 arch/arm/boot/dts/rk312x-pinctrl.dtsi | 22 ++++++++++++++++++
 arch/arm/boot/dts/rk312x.dtsi         | 32 +++++++++++++++++++++++++++
 4 files changed, 89 insertions(+)

diff --git a/arch/arm/boot/dts/rk3126-fpga.dts b/arch/arm/boot/dts/rk3126-fpga.dts
index 8eca90653017..01e7dc1eec0f 100755
--- a/arch/arm/boot/dts/rk3126-fpga.dts
+++ b/arch/arm/boot/dts/rk3126-fpga.dts
@@ -18,4 +18,17 @@
 	fiq-debugger {
 		status = "okay";
 	};
+
+	&fb {
+		rockchip,disp-mode = <ONE_DUAL>;
+        };
+
+	&rk_screen {
+		display-timings = <&disp_timings>;
+	};
+
+	&lcdc {
+		status = "okay";
+	};
+
 };
diff --git a/arch/arm/boot/dts/rk3126-sdk.dts b/arch/arm/boot/dts/rk3126-sdk.dts
index 87e4b706cad4..d57bf64a61b4 100755
--- a/arch/arm/boot/dts/rk3126-sdk.dts
+++ b/arch/arm/boot/dts/rk3126-sdk.dts
@@ -71,6 +71,28 @@
 	};
 };
 
+	&fb {
+		rockchip,disp-mode = <ONE_DUAL>;
+		rockchip,uboot-logo-on = <0>;
+	};
+
+	&rk_screen {
+		//display-timings = <&disp_timings>;
+	};
+
+	&lcdc {
+		status = "okay";
+
+		power_ctr: power_ctr {
+			rockchip,debug = <0>;
+			lcd_en: lcd_en {
+				rockchip,power_type = <GPIO>;
+				gpios = <&gpio1 GPIO_B3 GPIO_ACTIVE_HIGH>;
+				rockchip,delay = <10>;
+			};
+		};
+	};
+
 /include/ "rk818.dtsi"
 &rk818 {
 	gpios =<&gpio1 GPIO_B1 GPIO_ACTIVE_HIGH>,<&gpio1 GPIO_A1 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/rk312x-pinctrl.dtsi b/arch/arm/boot/dts/rk312x-pinctrl.dtsi
index 91e1e7ab570e..7a189857da9e 100755
--- a/arch/arm/boot/dts/rk312x-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rk312x-pinctrl.dtsi
@@ -792,6 +792,28 @@
 
 		};
 
+		gpio2_lcdc0 {
+			lcdc0_lcdc:lcdc0-lcdc {
+				rockchip,pins =
+						<LCDC0_DCLK>,
+						<LCDC0_DEN>,
+						<LCDC0_HSYNC>,
+						<LCDC0_VSYNC>;
+				rockchip,pull = <VALUE_PULL_DISABLE>;
+				rockchip,drive = <VALUE_DRV_DEFAULT>;
+			};
+
+			lcdc0_gpio:lcdc0-gpio {
+				rockchip,pins =
+						<FUNC_TO_GPIO(LCDC0_DCLK)>,
+						<FUNC_TO_GPIO(LCDC0_DEN)>,
+						<FUNC_TO_GPIO(LCDC0_HSYNC)>,
+						<FUNC_TO_GPIO(LCDC0_VSYNC)>;
+				rockchip,pull = <VALUE_PULL_DISABLE>;
+				rockchip,drive = <VALUE_DRV_DEFAULT>;
+			};
+
+		};
 
 		//to add 
 
diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index c25b9237113b..f4afa4422c21 100755
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -2,6 +2,7 @@
 #include <dt-bindings/suspend/rockchip-pm.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/clock/rk_system_status.h>
+#include <dt-bindings/rkfb/rk_fb.h>
 
 #include "skeleton.dtsi"
 #include "rk312x-clocks.dtsi"
@@ -19,6 +20,7 @@
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
+		lcdc = &lcdc;
 	//	spi0 = &spi0;
 	};
 
@@ -539,6 +541,36 @@
                 status = "disabled";
         };
 
+	fb: fb{
+		compatible = "rockchip,rk-fb";
+		rockchip,disp-mode = <ONE_DUAL>;
+	};
+
+	rk_screen: rk_screen{
+		compatible = "rockchip,screen";
+	};
+
+	lvds: lvds@20038000 {
+		compatible = "rockchip,rk31xx-lvds";
+		reg = <0x20038000 0x4000>;
+		clocks = <&clk_gates5 0>;
+		clock-names = "pclk_lvds";
+	};
+
+	lcdc: lcdc@1010e000 {
+		compatible = "rockchip,rk312x-lcdc";
+		rockchip,prop = <PRMRY>;
+		reg = <0x1010e000 0x2000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default", "gpio";
+		pinctrl-0 = <&lcdc0_lcdc>;
+		pinctrl-1 = <&lcdc0_gpio>;
+		clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
+		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
+		rockchip,iommu-enabled = <1>;
+		status = "disabled";
+	};
+
         vpu: vpu_service@10104000 {
 		compatible = "vpu_service";
 		reg = <0x10104000 0x800>;
-- 
2.34.1