From b029a0ec6a89efa96aabf759f7526ea2a2f30d6b Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 21 Jan 2014 12:38:07 +0000 Subject: [PATCH] [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS] No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMipsInstrFPU.td | 8 ++++---- lib/Target/Mips/MipsInstrFPU.td | 8 ++++---- lib/Target/Mips/MipsSchedule.td | 10 ++++++++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index 65d345dc3da..05c79beaef5 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -1,20 +1,20 @@ let isCodeGenOnly = 1, Predicates = [InMicroMips] in { -def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, +def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM_MM<0, 0x30>; def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, ADDS_FM_MM<0, 0xf0>; def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, ADDS_FM_MM<0, 0xb0>; -def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, +def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, ADDS_FM_MM<0, 0x70>; -def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, IIFadd, 1, fadd>, +def FADD_MM : MMRel, ADDS_FT<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>, ADDS_FM_MM<1, 0x30>; def FDIV_MM : MMRel, ADDS_FT<"div.d", AFGR64Opnd, IIFdivDouble, 0, fdiv>, ADDS_FM_MM<1, 0xf0>; def FMUL_MM : MMRel, ADDS_FT<"mul.d", AFGR64Opnd, IIFmulDouble, 1, fmul>, ADDS_FM_MM<1, 0xb0>; -def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, IIFadd, 0, fsub>, +def FSUB_MM : MMRel, ADDS_FT<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>, ADDS_FM_MM<1, 0x70>; def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM_MM<0x27>; diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 68a26c32a59..5c1bbf684ee 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -419,18 +419,18 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in { } /// Floating-point Aritmetic -def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, +def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, ADDS_FM<0x00, 16>; -defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; +defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>; defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>; defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; -def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, +def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, ADDS_FM<0x01, 16>; -defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; +defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; let Predicates = [HasMips32r2, HasStdEnc] in { def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>, diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index d31db0706c8..472722c1bcf 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -20,7 +20,6 @@ def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; def IIBranch : InstrItinClass; -def IIFadd : InstrItinClass; def IIFmulSingle : InstrItinClass; def IIFmulDouble : InstrItinClass; def IIFdivSingle : InstrItinClass; @@ -37,6 +36,8 @@ def II_ABS : InstrItinClass; def II_ADDI : InstrItinClass; def II_ADDIU : InstrItinClass; def II_ADDU : InstrItinClass; +def II_ADD_D : InstrItinClass; +def II_ADD_S : InstrItinClass; def II_AND : InstrItinClass; def II_ANDI : InstrItinClass; def II_CEIL : InstrItinClass; @@ -112,6 +113,8 @@ def II_SRAV : InstrItinClass; def II_SRL : InstrItinClass; def II_SRLV : InstrItinClass; def II_SUBU : InstrItinClass; +def II_SUB_D : InstrItinClass; +def II_SUB_S : InstrItinClass; def II_TRUNC : InstrItinClass; def II_XOR : InstrItinClass; def II_XORI : InstrItinClass; @@ -200,7 +203,10 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, - InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>, -- 2.34.1