From b081f067457cc28503326f4a7d90b212087c6acc Mon Sep 17 00:00:00 2001
From: Alex Lorenz <arphaman@gmail.com>
Date: Tue, 18 Aug 2015 22:57:36 +0000
Subject: [PATCH] MIR Parser: Return true on error when parsing standalone
 registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245384 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/MIRParser/MIParser.cpp            |  4 ++--
 .../MIR/X86/standalone-register-error.mir     | 24 +++++++++++++++++++
 2 files changed, 26 insertions(+), 2 deletions(-)
 create mode 100644 test/CodeGen/MIR/X86/standalone-register-error.mir

diff --git a/lib/CodeGen/MIRParser/MIParser.cpp b/lib/CodeGen/MIRParser/MIParser.cpp
index 20581a1692f..3ec039285b3 100644
--- a/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/lib/CodeGen/MIRParser/MIParser.cpp
@@ -647,7 +647,7 @@ bool MIParser::parseStandaloneNamedRegister(unsigned &Reg) {
   if (Token.isNot(MIToken::NamedRegister))
     return error("expected a named register");
   if (parseRegister(Reg))
-    return 0;
+    return true;
   lex();
   if (Token.isNot(MIToken::Eof))
     return error("expected end of string after the register reference");
@@ -659,7 +659,7 @@ bool MIParser::parseStandaloneVirtualRegister(unsigned &Reg) {
   if (Token.isNot(MIToken::VirtualRegister))
     return error("expected a virtual register");
   if (parseRegister(Reg))
-    return 0;
+    return true;
   lex();
   if (Token.isNot(MIToken::Eof))
     return error("expected end of string after the register reference");
diff --git a/test/CodeGen/MIR/X86/standalone-register-error.mir b/test/CodeGen/MIR/X86/standalone-register-error.mir
new file mode 100644
index 00000000000..f17451bfc89
--- /dev/null
+++ b/test/CodeGen/MIR/X86/standalone-register-error.mir
@@ -0,0 +1,24 @@
+# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
+--- |
+  define i32 @test(i32 %a) {
+  body:
+    ret i32 %a
+  }
+...
+---
+name:            test
+isSSA:           true
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gr32 }
+liveins:
+# CHECK: [[@LINE+1]]:13: unknown register name 'register'
+  - { reg: '%register', virtual-reg: '%0' }
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
+...
-- 
2.34.1