From b0d21ef20c29f4ea46d21b488f17feaa6a8760e1 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 8 Mar 2006 04:25:59 +0000 Subject: [PATCH] Change the interface for getting a target HazardRecognizer to be more clean. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 9 +++----- include/llvm/CodeGen/SelectionDAGISel.h | 6 ++--- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 2 +- lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 23 +++++++++---------- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 +++---- lib/Target/PowerPC/PPCHazardRecognizers.cpp | 10 ++++---- lib/Target/PowerPC/PPCHazardRecognizers.h | 2 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 7 +++--- 8 files changed, 29 insertions(+), 38 deletions(-) diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index a506b82dae5..25b62e2896c 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -57,10 +57,6 @@ namespace llvm { NoopHazard, // This instruction can't be emitted, and needs noops. }; - /// StartBasicBlock - This is called when a new basic block is started. - /// - virtual void StartBasicBlock() {} - /// getHazardType - Return the hazard type of emitting this node. There are /// three possible results. Either: /// * NoHazard: it is legal to issue this instruction on this cycle. @@ -410,10 +406,11 @@ namespace llvm { MachineBasicBlock *BB); /// createTDListDAGScheduler - This creates a top-down list scheduler with - /// the specified hazard recognizer. + /// the specified hazard recognizer. This takes ownership of the hazard + /// recognizer and deletes it when done. ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB, - HazardRecognizer &HR); + HazardRecognizer *HR); } #endif diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index ffaa1c6a35c..1bdf055c477 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -62,9 +62,9 @@ public: return true; } - /// GetTargetHazardRecognizer - Return the hazard recognizer to use for this - /// target when scheduling the DAG. - virtual HazardRecognizer &GetTargetHazardRecognizer(); + /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer + /// to use for this target when scheduling the DAG. + virtual HazardRecognizer *CreateTargetHazardRecognizer(); protected: /// Pick a safe ordering and emit instructions for each target node in the diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index c9455a00944..d6255db9c1c 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -14,9 +14,9 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "sched" +#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 93198d1093b..e089d0bc0f6 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -178,7 +178,7 @@ private: bool isBottomUp; /// HazardRec - The hazard recognizer to use. - HazardRecognizer &HazardRec; + HazardRecognizer *HazardRec; typedef std::priority_queue, ls_rr_sort> AvailableQueueTy; @@ -186,7 +186,7 @@ private: public: ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb, const TargetMachine &tm, bool isbottomup, - HazardRecognizer &HR) + HazardRecognizer *HR) : ScheduleDAG(listSchedulingBURR, dag, bb, tm), CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup), HazardRec(HR) { @@ -199,6 +199,7 @@ public: delete SU; SU = NextSU; } + delete HazardRec; } void Schedule(); @@ -413,12 +414,10 @@ void ScheduleDAGList::ListScheduleTopDown() { // Available queue. AvailableQueueTy Available; - HazardRec.StartBasicBlock(); - // Emit the entry node first. SUnit *Entry = SUnitMap[DAG.getEntryNode().Val]; ScheduleNodeTopDown(Available, Entry); - HazardRec.EmitInstruction(Entry->Node); + HazardRec->EmitInstruction(Entry->Node); // All leaves to Available queue. for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) { @@ -446,7 +445,7 @@ void ScheduleDAGList::ListScheduleTopDown() { N->getOpcode() < ISD::BUILTIN_OP_END && i != e; ++i) N = CurNode->FlaggedNodes[i]; - HazardRecognizer::HazardType HT = HazardRec.getHazardType(N); + HazardRecognizer::HazardType HT = HazardRec->getHazardType(N); if (HT == HazardRecognizer::NoHazard) { FoundNode = CurNode; break; @@ -467,19 +466,19 @@ void ScheduleDAGList::ListScheduleTopDown() { // If we found a node to schedule, do it now. if (FoundNode) { ScheduleNodeTopDown(Available, FoundNode); - HazardRec.EmitInstruction(FoundNode->Node); + HazardRec->EmitInstruction(FoundNode->Node); } else if (!HasNoopHazards) { // Otherwise, we have a pipeline stall, but no other problem, just advance // the current cycle and try again. DEBUG(std::cerr << "*** Advancing cycle, no work to do\n"); - HazardRec.AdvanceCycle(); + HazardRec->AdvanceCycle(); ++NumStalls; } else { // Otherwise, we have no instructions to issue and we have instructions // that will fault if we don't do this right. This is the case for // processors without pipeline interlocks and other cases. DEBUG(std::cerr << "*** Emitting noop\n"); - HazardRec.EmitNoop(); + HazardRec->EmitNoop(); Sequence.push_back(0); // NULL SUnit* -> noop ++NumNoops; } @@ -691,14 +690,14 @@ void ScheduleDAGList::Schedule() { llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB) { - HazardRecognizer HR; - return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true, HR); + return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true, + new HazardRecognizer()); } /// createTDListDAGScheduler - This creates a top-down list scheduler with the /// specified hazard recognizer. ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB, - HazardRecognizer &HR) { + HazardRecognizer *HR) { return new ScheduleDAGList(DAG, BB, DAG.getTarget(), false, HR); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 3e97494a26e..b0eae94e925 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2474,17 +2474,15 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { SL = createBURRListDAGScheduler(DAG, BB); break; case listSchedulingTD: - SL = createTDListDAGScheduler(DAG, BB, GetTargetHazardRecognizer()); + SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer()); break; } BB = SL->Run(); delete SL; } -HazardRecognizer &SelectionDAGISel:: -GetTargetHazardRecognizer() { - static HazardRecognizer DefaultRecognizer; - return DefaultRecognizer; +HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { + return new HazardRecognizer(); } /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 852b9c8e32d..203f116135b 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -50,6 +50,10 @@ using namespace llvm; // e.g. integer divides that only execute in the second slot. // +PPCHazardRecognizer970::PPCHazardRecognizer970() { + EndDispatchGroup(); +} + void PPCHazardRecognizer970::EndDispatchGroup() { DEBUG(std::cerr << "=== Start of dispatch group\n"); // Pipeline units. @@ -117,12 +121,6 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode) { return FXU; } - -/// StartBasicBlock - Initiate a new dispatch group. -void PPCHazardRecognizer970::StartBasicBlock() { - EndDispatchGroup(); -} - /// isLoadOfStoredAddress - If we have a load from the previously stored pointer /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. bool PPCHazardRecognizer970:: diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.h b/lib/Target/PowerPC/PPCHazardRecognizers.h index 5f7bb1bac26..fb1f88e0449 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.h +++ b/lib/Target/PowerPC/PPCHazardRecognizers.h @@ -52,7 +52,7 @@ class PPCHazardRecognizer970 : public HazardRecognizer { unsigned StoreSize; public: - virtual void StartBasicBlock(); + PPCHazardRecognizer970(); virtual HazardType getHazardType(SDNode *Node); virtual void EmitInstruction(SDNode *Node); virtual void AdvanceCycle(); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 5c74a7ba6cd..4c2d4af6f92 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -41,7 +41,6 @@ namespace { class PPCDAGToDAGISel : public SelectionDAGISel { PPCTargetLowering PPCLowering; unsigned GlobalBaseReg; - PPCHazardRecognizer970 PPC970HR; public: PPCDAGToDAGISel(TargetMachine &TM) : SelectionDAGISel(PPCLowering), PPCLowering(TM) {} @@ -125,12 +124,12 @@ namespace { return "PowerPC DAG->DAG Pattern Instruction Selection"; } - /// GetTargetHazardRecognizer - Return the hazard recognizer to use for this + /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for this /// target when scheduling the DAG. - virtual HazardRecognizer &GetTargetHazardRecognizer() { + virtual HazardRecognizer *CreateTargetHazardRecognizer() { // Should use subtarget info to pick the right hazard recognizer. For // now, always return a PPC970 recognizer. - return PPC970HR; + return new PPCHazardRecognizer970(); } // Include the pieces autogenerated from the target description. -- 2.34.1