From b210c306c9f49082297d5f511b2257bb0698fa07 Mon Sep 17 00:00:00 2001
From: =?utf8?q?=E9=BB=84=E6=B6=9B?= <huangtao@rock-chips.com>
Date: Tue, 17 Jun 2014 10:40:00 +0800
Subject: [PATCH] ARM: rockchip: ddr_rk30: fix compilation warning

---
 arch/arm/mach-rockchip/ddr_rk30.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-rockchip/ddr_rk30.c b/arch/arm/mach-rockchip/ddr_rk30.c
index c615fce93475..072b9d6aa646 100755
--- a/arch/arm/mach-rockchip/ddr_rk30.c
+++ b/arch/arm/mach-rockchip/ddr_rk30.c
@@ -3733,6 +3733,7 @@ static void _ddr_set_auto_self_refresh(bool en)
 
 #define PERI_PCLK_DIV_MASK 0x3
 #define PERI_PCLK_DIV_OFF 12
+#if 0
 static __sramdata u32 cru_sel32_sram;
 static void __sramfunc ddr_suspend(void)
 {
@@ -3807,6 +3808,7 @@ static void __sramfunc ddr_resume(void)
 
     ddr_selfrefresh_exit();
 }
+#endif
 
 //»ñÈ¡ÈÝÁ¿£¬·µ»Ø×Ö½ÚÊý
 static uint32 ddr_get_cap(void)
@@ -3829,6 +3831,7 @@ static uint32 ddr_get_cap(void)
     return cap;
 }
 
+#if 0
 static void ddr_reg_save(void)
 {
     //PCTLR
@@ -3910,6 +3913,7 @@ static __attribute__((aligned(4))) __sramdata uint32 ddr_reg_resume[] =
 {
 #include "ddr_reg_resume.inc"
 };
+#endif
 
 static int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
 {
-- 
2.34.1