From b26cc705b0ef3540c4deaaa497c8519cdf66e408 Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 29 Apr 2015 15:11:07 +0000 Subject: [PATCH] [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions Differential Revision: http://reviews.llvm.org/D8704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236111 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrFormats.td | 28 ++++++++++++++++++++ lib/Target/Mips/MicroMips32r6InstrInfo.td | 11 +++++++- lib/Target/Mips/MipsInstrInfo.td | 9 ++++--- test/MC/Disassembler/Mips/micromips32r6.txt | 6 +++++ test/MC/Mips/micromips32r6/valid.s | 3 +++ 5 files changed, 52 insertions(+), 5 deletions(-) diff --git a/lib/Target/Mips/MicroMips32r6InstrFormats.td b/lib/Target/Mips/MicroMips32r6InstrFormats.td index 3e20fe51b08..ce21dd2e57f 100644 --- a/lib/Target/Mips/MicroMips32r6InstrFormats.td +++ b/lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -42,3 +42,31 @@ class CACHE_PREF_FM_MMR6 opgroup, bits<4> funct> : MipsR6Inst { let Inst{15-12} = funct; let Inst{11-0} = addr{11-0}; } + +class ARITH_FM_MMR6 funct> : MMR6Arch { + bits<5> rd; + bits<5> rt; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10} = 0; + let Inst{9-0} = funct; +} + +class ADDI_FM_MMR6 op> : MMR6Arch { + bits<5> rt; + bits<5> rs; + bits<16> imm16; + + bits<32> Inst; + + let Inst{31-26} = op; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-0} = imm16; +} diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index c27b6dd38f3..9d6f0dfe306 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -16,7 +16,9 @@ // Instruction Encodings // //===----------------------------------------------------------------------===// - +class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>; +class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>; +class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>; class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; @@ -29,6 +31,10 @@ class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>; // //===----------------------------------------------------------------------===// +class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; +class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>; +class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; + class BC_MMR6_DESC_BASE : BRANCH_DESC_BASE, MMR6Arch { dag InOperandList = (ins opnd:$offset); @@ -72,6 +78,9 @@ class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>; //===----------------------------------------------------------------------===// let DecoderNamespace = "MicroMips32r6" in { +def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; +def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6; +def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6; def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index db890382548..5608e00caa9 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1123,8 +1123,9 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), /// Arithmetic Instructions (ALU Immediate) let AdditionalPredicates = [NotInMicroMips] in { -def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, - add>, ADDI_FM<0x9>, IsAsCheapAsAMove; +def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd, + II_ADDIU, immSExt16, add>, + ADDI_FM<0x9>, IsAsCheapAsAMove; } def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; @@ -1145,7 +1146,7 @@ def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { /// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, +def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, ADD_FM<0, 0x21>; def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, ADD_FM<0, 0x23>; @@ -1153,7 +1154,7 @@ def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; -def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; +def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>; def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>; def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; diff --git a/test/MC/Disassembler/Mips/micromips32r6.txt b/test/MC/Disassembler/Mips/micromips32r6.txt index b612634e488..bb5fd9bf18a 100644 --- a/test/MC/Disassembler/Mips/micromips32r6.txt +++ b/test/MC/Disassembler/Mips/micromips32r6.txt @@ -1,5 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s +0x00 0xa4 0x19 0x10 # CHECK: add $3, $4, $5 + +0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234 + +0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5 + # CHECK: balc 14572256 0xb4 0x37 0x96 0xb8 diff --git a/test/MC/Mips/micromips32r6/valid.s b/test/MC/Mips/micromips32r6/valid.s index b08dcafa051..94d777af169 100644 --- a/test/MC/Mips/micromips32r6/valid.s +++ b/test/MC/Mips/micromips32r6/valid.s @@ -1,6 +1,9 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s .set noat + add $3, $4, $5 # CHECK: add $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x10] + addiu $3, $4, 1234 # CHECK: addiu $3, $4, 1234 # encoding: [0x30,0x64,0x04,0xd2] + addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50] balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c] -- 2.34.1