From b449a68146c7188a20bba11db19229a5cb46938a Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Sat, 28 Mar 2009 17:03:24 +0000 Subject: [PATCH] Make code a bit less brittle by no hardcoding the number of operands in an address in so many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67945 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86CodeEmitter.cpp | 18 ++++++++++++------ lib/Target/X86/X86FloatingPoint.cpp | 3 ++- lib/Target/X86/X86InstrInfo.cpp | 2 +- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index bbe063b4f82..f7c8c8de451 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -32,6 +32,9 @@ #include "llvm/Target/TargetOptions.h" using namespace llvm; +// FIXME: This should be some header +static const int X86AddrNumOperands = 4; + STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { @@ -642,8 +645,10 @@ void Emitter::emitInstruction(const MachineInstr &MI, } case X86II::MRMDestMem: { MCE.emitByte(BaseOpcode); - emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg())); - CurOp += 5; + emitMemModRMByte(MI, CurOp, + getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands) + .getReg())); + CurOp += X86AddrNumOperands + 1; if (CurOp != NumOps) emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; @@ -659,12 +664,13 @@ void Emitter::emitInstruction(const MachineInstr &MI, break; case X86II::MRMSrcMem: { - intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0; + intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ? + X86InstrInfo::sizeOfImm(Desc) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()), PCAdj); - CurOp += 5; + CurOp += X86AddrNumOperands + 1; if (CurOp != NumOps) emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); break; @@ -714,13 +720,13 @@ void Emitter::emitInstruction(const MachineInstr &MI, case X86II::MRM2m: case X86II::MRM3m: case X86II::MRM4m: case X86II::MRM5m: case X86II::MRM6m: case X86II::MRM7m: { - intptr_t PCAdj = (CurOp+4 != NumOps) ? + intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ? (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0; MCE.emitByte(BaseOpcode); emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, PCAdj); - CurOp += 4; + CurOp += X86AddrNumOperands; if (CurOp != NumOps) { const MachineOperand &MO = MI.getOperand(CurOp++); diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 8862428b226..dee57176d9f 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -616,9 +616,10 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { /// handleOneArgFP - fst , ST(0) /// void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { + const int X86AddrNumOperands = 4; MachineInstr *MI = I; unsigned NumOps = MI->getDesc().getNumOperands(); - assert((NumOps == 5 || NumOps == 1) && + assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) && "Can only handle fst* & ftst instructions!"); // Is this the last use of the source register? diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index f5c3d1db687..86d64a6327e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -763,7 +763,7 @@ unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, MI->getOperand(2).getReg() == 0 && MI->getOperand(3).getImm() == 0) { FrameIndex = MI->getOperand(0).getIndex(); - return MI->getOperand(4).getReg(); + return MI->getOperand(X86AddrNumOperands).getReg(); } break; } -- 2.34.1