From b52a26e7321f63e9176b48ae6eb1a5d0eaa9f3f2 Mon Sep 17 00:00:00 2001 From: lw Date: Tue, 7 Feb 2012 14:34:24 +0800 Subject: [PATCH] rk30:modify table key size to make iomux code aligned --- arch/arm/mach-rk30/include/mach/iomux.h | 366 ++++++++++++------------ arch/arm/mach-rk30/iomux.c | 298 +++++++++---------- 2 files changed, 332 insertions(+), 332 deletions(-) diff --git a/arch/arm/mach-rk30/include/mach/iomux.h b/arch/arm/mach-rk30/include/mach/iomux.h index 8572b62ec5ad..518a2ba50f49 100755 --- a/arch/arm/mach-rk30/include/mach/iomux.h +++ b/arch/arm/mach-rk30/include/mach/iomux.h @@ -22,19 +22,19 @@ #define GPIO0A_GPIO0A7 0 #define GPIO0A_I2S_8CH_SDI 1 #define GPIO0A_GPIO0A6 0 -#define GPIO0A_HOST_DRV_VBUS 1 +#define GPIO0A_HOST_DRV_VBUS 1 #define GPIO0A_GPIO0A5 0 #define GPIO0A_OTG_DRV_VBUS 1 #define GPIO0A_GPIO0A4 0 -#define GPIO0A_PWM1 1 +#define GPIO0A_PWM1 1 #define GPIO0A_GPIO0A3 0 -#define GPIO0A_PWM0 1 +#define GPIO0A_PWM0 1 #define GPIO0A_GPIO0A2 0 #define GPIO0A_HDMI_I2C_SDA 1 #define GPIO0A_GPIO0A1 0 #define GPIO0A_HDMI_I2C_SCL 1 #define GPIO0A_GPIO0A0 0 -#define GPIO0A_HDMI_HOT_PLUG_IN 1 +#define GPIO0A_HDMI_HOT_PLUG_IN 1 //GPIO0B @@ -47,9 +47,9 @@ #define GPIO0B_GPIO0B4 0 #define GPIO0B_I2S_8CH_SDO0 1 #define GPIO0B_GPIO0B3 0 -#define GPIO0B_I2S_8CH_LRCK_TX 1 +#define GPIO0B_I2S_8CH_LRCK_TX 1 #define GPIO0B_GPIO0B2 0 -#define GPIO0B_I2S_8CH_LRCK_RX 1 +#define GPIO0B_I2S_8CH_LRCK_RX 1 #define GPIO0B_GPIO0B1 0 #define GPIO0B_I2S_8CH_SCLK 1 #define GPIO0B_GPIO0B0 0 @@ -68,11 +68,11 @@ #define GPIO0C_GPIO0C4 0 #define GPIO0C_I2S1_2CH_SDI 1 #define GPIO0C_GPIO0C3 0 -#define GPIO0C_I2S1_2CH_LRCK_TX 1 +#define GPIO0C_I2S1_2CH_LRCK_TX 1 #define GPIO0C_GPIO0C2 0 -#define GPIO0C_I2S_8CH_LRCK_RX 1 +#define GPIO0C_I2S_8CH_LRCK_RX 1 #define GPIO0C_GPIO0C1 0 -#define GPIO0C_I2S1_2CH_SCLK 1 +#define GPIO0C_I2S1_2CH_SCLK 1 #define GPIO0C_GPIO0C0 0 #define GPIO0C_I2S1_2CH_CLK 1 @@ -80,9 +80,9 @@ //GPIO0D #define GPIO0D_GPIO0D7 0 -#define GPIO0D_PWM3 1 +#define GPIO0D_PWM3 1 #define GPIO0D_GPIO0D6 0 -#define GPIO0D_PWM2 1 +#define GPIO0D_PWM2 1 #define GPIO0D_GPIO0D5 0 #define GPIO0D_I2S2_2CH_SDO 1 #define GPIO0D_SMC_ADDR1 2 @@ -90,13 +90,13 @@ #define GPIO0D_I2S1_2CH_SDI 1 #define GPIO0D_SMC_ADDR0 2 #define GPIO0D_GPIO0D3 0 -#define GPIO0D_I2S1_2CH_LRCK_TX 1 +#define GPIO0D_I2S1_2CH_LRCK_TX 1 #define GPIO0D_SMC_ADV_N 2 #define GPIO0D_GPIO0D2 0 -#define GPIO0D_I2S1_2CH_LRCK_RX 1 +#define GPIO0D_I2S1_2CH_LRCK_RX 1 #define GPIO0D_SMC_OE_N 2 #define GPIO0D_GPIO0D1 0 -#define GPIO0D_I2S2_2CH_SCLK 1 +#define GPIO0D_I2S2_2CH_SCLK 1 #define GPIO0D_SMC_WE_N 2 #define GPIO0D_GPIO0D0 0 #define GPIO0D_I2S2_2CH_CLK 1 @@ -154,7 +154,7 @@ #define GPIO1C_RMII_RXD1 2 #define GPIO1C_GPIO1C5 0 #define GPIO1C_CIF_DATA7 1 -#define GPIO1C_RMII_CRS_DVALID 2 +#define GPIO1C_RMII_CRS_DVALID 2 #define GPIO1C_GPIO1C4 0 #define GPIO1C_CIF_DATA6 1 #define GPIO1C_RMII_RX_ERR 2 @@ -309,9 +309,9 @@ //GPIO3A #define GPIO3A_GPIO3A7 0 -#define GPIO3A_SDMMC0_WRITE_PRT 1 +#define GPIO3A_SDMMC0_WRITE_PRT 1 #define GPIO3A_GPIO3A6 0 -#define GPIO3A_SDMMC0_RSTN_OUT 1 +#define GPIO3A_SDMMC0_RSTN_OUT 1 #define GPIO4A_GPIO4A5 0 #define GPIO4A_I2C4_SCL 1 #define GPIO3A_GPIO3A4 0 @@ -328,9 +328,9 @@ //GPIO3B #define GPIO3B_GPIO3B7 0 -#define GPIO3B_SDMMC0_WRITE_PRT 1 +#define GPIO3B_SDMMC0_WRITE_PRT 1 #define GPIO3B_GPIO3B6 0 -#define GPIO3B_SDMMC0_DETECT_N 1 +#define GPIO3B_SDMMC0_DETECT_N 1 #define GPIO3B_GPIO3B5 0 #define GPIO3B_SDMMC0_DATA3 1 #define GPIO3B_GPIO3B4 0 @@ -342,16 +342,16 @@ #define GPIO3B_GPIO3B1 0 #define GPIO3B_SDMMC0_CMD 1 #define GPIO3B_GPIO3B0 0 -#define GPIO3B_SDMMC0_CLKOUT 1 +#define GPIO3B_SDMMC0_CLKOUT 1 //GPIO3C #define GPIO3C_GPIO3C7 0 -#define GPIO3C_SDMMC1_WRITE_PRT 1 +#define GPIO3C_SDMMC1_WRITE_PRT 1 #define GPIO3C_GPIO3C6 0 -#define GPIO3C_SDMMC1_DETECT_N 1 +#define GPIO3C_SDMMC1_DETECT_N 1 #define GPIO3C_GPIO3C5 0 -#define GPIO3C_SDMMC1_CLKOUT 1 +#define GPIO3C_SDMMC1_CLKOUT 1 #define GPIO3C_GPIO3C4 0 #define GPIO3C_SDMMC1_DATA3 1 #define GPIO3C_GPIO3C3 0 @@ -379,9 +379,9 @@ #define GPIO3D_GPIO3D2 0 #define GPIO3D_SDMMC1_INT_N 1 #define GPIO3D_GPIO3D1 0 -#define GPIO3D_SDMMC1_BACKEND_PWR 1 +#define GPIO3D_SDMMC1_BACKEND_PWR 1 #define GPIO3D_GPIO3D0 0 -#define GPIO3D_SDMMC1_PWR_EN 1 +#define GPIO3D_SDMMC1_PWR_EN 1 //GPIO4A @@ -416,7 +416,7 @@ #define GPIO4B_FLASH_CSN4 1 #define GPIO4B_GPIO4B2 0 #define GPIO4B_FLASH_CSN3 1 -#define GPIO4B_EMMC_RSTN_OUT 2 +#define GPIO4B_EMMC_RSTN_OUT 2 #define GPIO4B_GPIO4B1 0 #define GPIO4B_FLASH_CSN2 1 #define GPIO4B_EMMC_CMD 2 @@ -480,11 +480,11 @@ //GPIO6B #define GPIO6B_GPIO6B7 0 -#define GPIO6B_TEST_CLOCK_OUT 1 +#define GPIO6B_TEST_CLOCK_OUT 1 -#define DEFAULT 0 -#define INITIAL 1 +#define DEFAULT 0 +#define INITIAL 1 #define GRF_GPIO0L_DIR 0x0000 @@ -579,230 +579,230 @@ //GPIO0A -#define GPIO0A7_I2S8CHSDI_NAME "gpio0a7_i2s8chsdi_name" -#define GPIO0A6_HOSTDRVVBUS_NAME "gpio0a6_hostdrvvbus_name" -#define GPIO0A5_OTGDRVVBUS_NAME "gpio0a5_otgdrvvbus_name" -#define GPIO0A4_PWM1_NAME "gpio0a4_pwm1_name" -#define GPIO0A3_PWM0_NAME "gpio0a3_pwm0_name" -#define GPIO0A2_HDMII2CSDA_NAME "gpio0a2_hdmii2csda_name" -#define GPIO0A1_HDMII2CSCL_NAME "gpio0a1_hdmii2cscl_name" -#define GPIO0A0_HDMIHOTPLUGIN_NAME "gpio0a0_hdmihotplugin_name" +#define GPIO0A7_I2S8CHSDI_NAME "gpio0a7_i2s8chsdi_name" +#define GPIO0A6_HOSTDRVVBUS_NAME "gpio0a6_hostdrvvbus_name" +#define GPIO0A5_OTGDRVVBUS_NAME "gpio0a5_otgdrvvbus_name" +#define GPIO0A4_PWM1_NAME "gpio0a4_pwm1_name" +#define GPIO0A3_PWM0_NAME "gpio0a3_pwm0_name" +#define GPIO0A2_HDMII2CSDA_NAME "gpio0a2_hdmii2csda_name" +#define GPIO0A1_HDMII2CSCL_NAME "gpio0a1_hdmii2cscl_name" +#define GPIO0A0_HDMIHOTPLUGIN_NAME "gpio0a0_hdmihotplugin_name" //GPIO0B -#define GPIO0B7_I2S8CHSDO3_NAME "gpio0b7_i2s8chsdo3_name" -#define GPIO0B6_I2S8CHSDO2_NAME "gpio0b6_i2s8chsdo2_name" -#define GPIO0B5_I2S8CHSDO1_NAME "gpio0b5_i2s8chsdo1_name" -#define GPIO0B4_I2S8CHSDO0_NAME "gpio0b4_i2s8chsdo0_name" -#define GPIO0B3_I2S8CHLRCKTX_NAME "gpio0b3_i2s8chlrcktx_name" -#define GPIO0B2_I2S8CHLRCKRX_NAME "gpio0b2_i2s8chlrckrx_name" -#define GPIO0B1_I2S8CHSCLK_NAME "gpio0b1_i2s8chsclk_name" -#define GPIO0B0_I2S8CHCLK_NAME "gpio0b0_i2s8chclk_name" +#define GPIO0B7_I2S8CHSDO3_NAME "gpio0b7_i2s8chsdo3_name" +#define GPIO0B6_I2S8CHSDO2_NAME "gpio0b6_i2s8chsdo2_name" +#define GPIO0B5_I2S8CHSDO1_NAME "gpio0b5_i2s8chsdo1_name" +#define GPIO0B4_I2S8CHSDO0_NAME "gpio0b4_i2s8chsdo0_name" +#define GPIO0B3_I2S8CHLRCKTX_NAME "gpio0b3_i2s8chlrcktx_name" +#define GPIO0B2_I2S8CHLRCKRX_NAME "gpio0b2_i2s8chlrckrx_name" +#define GPIO0B1_I2S8CHSCLK_NAME "gpio0b1_i2s8chsclk_name" +#define GPIO0B0_I2S8CHCLK_NAME "gpio0b0_i2s8chclk_name" //GPIO0C -#define GPIO0C7_TRACECTL_SMCADDR3_NAME "gpio0c7_tracectl_smcaddr3_name" -#define GPIO0C6_TRACECLK_SMCADDR2_NAME "gpio0c6_traceclk_smcaddr2_name" -#define GPIO0C5_I2S12CHSDO_NAME "gpio0c5_i2s12chsdo_name" -#define GPIO0C4_I2S12CHSDI_NAME "gpio0c4_i2s12chsdi_name" -#define GPIO0C3_I2S12CHLRCKTX_NAME "gpio0c3_i2s12chlrcktx_name" -#define GPIO0C2_I2S8CHLRCKRX_NAME "gpio0c2_i2s8chlrckrx_name" -#define GPIO0C1_I2S12CHSCLK_NAME "gpio0c1_i2s12chsclk_name" -#define GPIO0C0_I2S12CHCLK_NAME "gpio0c0_i2s12chclk_name" +#define GPIO0C7_TRACECTL_SMCADDR3_NAME "gpio0c7_tracectl_smcaddr3_name" +#define GPIO0C6_TRACECLK_SMCADDR2_NAME "gpio0c6_traceclk_smcaddr2_name" +#define GPIO0C5_I2S12CHSDO_NAME "gpio0c5_i2s12chsdo_name" +#define GPIO0C4_I2S12CHSDI_NAME "gpio0c4_i2s12chsdi_name" +#define GPIO0C3_I2S12CHLRCKTX_NAME "gpio0c3_i2s12chlrcktx_name" +#define GPIO0C2_I2S8CHLRCKRX_NAME "gpio0c2_i2s8chlrckrx_name" +#define GPIO0C1_I2S12CHSCLK_NAME "gpio0c1_i2s12chsclk_name" +#define GPIO0C0_I2S12CHCLK_NAME "gpio0c0_i2s12chclk_name" //GPIO0D -#define GPIO0D7_PWM3_NAME "gpio0d7_pwm3_name" -#define GPIO0D6_PWM2_NAME "gpio0d6_pwm2_name" -#define GPIO0D5_I2S22CHSDO_SMCADDR1_NAME "gpio0d5_i2s22chsdo_smcaddr1_name" -#define GPIO0D4_I2S12CHSDI_SMCADDR0_NAME "gpio0d4_i2s12chsdi_smcaddr0_name" -#define GPIO0D3_I2S12CHLRCKTX_SMCADVN_NAME "gpio0d3_i2s12chlrcktx_smcadvn_name" -#define GPIO0D2_I2S12CHLRCKRX_SMCOEN_NAME "gpio0d2_i2s12chlrckrx_smcoen_name" -#define GPIO0D1_I2S22CHSCLK_SMCWEN_NAME "gpio0d1_i2s22chsclk_smcwen_name" -#define GPIO0D0_I2S22CHCLK_SMCCSN0_NAME "gpio0d0_i2s22chclk_smccsn0_name" +#define GPIO0D7_PWM3_NAME "gpio0d7_pwm3_name" +#define GPIO0D6_PWM2_NAME "gpio0d6_pwm2_name" +#define GPIO0D5_I2S22CHSDO_SMCADDR1_NAME "gpio0d5_i2s22chsdo_smcaddr1_name" +#define GPIO0D4_I2S12CHSDI_SMCADDR0_NAME "gpio0d4_i2s12chsdi_smcaddr0_name" +#define GPIO0D3_I2S12CHLRCKTX_SMCADVN_NAME "gpio0d3_i2s12chlrcktx_smcadvn_name" +#define GPIO0D2_I2S12CHLRCKRX_SMCOEN_NAME "gpio0d2_i2s12chlrckrx_smcoen_name" +#define GPIO0D1_I2S22CHSCLK_SMCWEN_NAME "gpio0d1_i2s22chsclk_smcwen_name" +#define GPIO0D0_I2S22CHCLK_SMCCSN0_NAME "gpio0d0_i2s22chclk_smccsn0_name" //GPIO1A -#define GPIO1A7_UART1RTSN_SPI0TXD_NAME "gpio1a7_uart1rtsn_spi0txd_name" -#define GPIO1A6_UART1CTSN_SPI0RXD_NAME "gpio1a6_uart1ctsn_spi0rxd_name" -#define GPIO1A5_UART1SOUT_SPI0CLK_NAME "gpio1a5_uart1sout_spi0clk_name" -#define GPIO1A4_UART1SIN_SPI0CSN0_NAME "gpio1a4_uart1sin_spi0csn0_name" -#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name" -#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name" -#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name" -#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name" +#define GPIO1A7_UART1RTSN_SPI0TXD_NAME "gpio1a7_uart1rtsn_spi0txd_name" +#define GPIO1A6_UART1CTSN_SPI0RXD_NAME "gpio1a6_uart1ctsn_spi0rxd_name" +#define GPIO1A5_UART1SOUT_SPI0CLK_NAME "gpio1a5_uart1sout_spi0clk_name" +#define GPIO1A4_UART1SIN_SPI0CSN0_NAME "gpio1a4_uart1sin_spi0csn0_name" +#define GPIO1A3_UART0RTSN_NAME "gpio1a3_uart0rtsn_name" +#define GPIO1A2_UART0CTSN_NAME "gpio1a2_uart0ctsn_name" +#define GPIO1A1_UART0SOUT_NAME "gpio1a1_uart0sout_name" +#define GPIO1A0_UART0SIN_NAME "gpio1a0_uart0sin_name" //GPIO1B -#define GPIO1B7_CIFDATA11_NAME "gpio1b7_cifdata11_name" -#define GPIO1B6_CIFDATA10_NAME "gpio1b6_cifdata10_name" -#define GPIO1B5_CIF0DATA1_NAME "gpio1b5_cif0data1_name" -#define GPIO1B4_CIF0DATA0_NAME "gpio1b4_cif0data0_name" -#define GPIO1B3_CIF0CLKOUT_NAME "gpio1b3_cif0clkout_name" -#define GPIO1B2_SPDIFTX_NAME "gpio1b2_spdiftx_name" -#define GPIO1B1_UART2SOUT_NAME "gpio1b1_uart2sout_name" -#define GPIO1B0_UART2SIN_NAME "gpio1b0_uart2sin_name" +#define GPIO1B7_CIFDATA11_NAME "gpio1b7_cifdata11_name" +#define GPIO1B6_CIFDATA10_NAME "gpio1b6_cifdata10_name" +#define GPIO1B5_CIF0DATA1_NAME "gpio1b5_cif0data1_name" +#define GPIO1B4_CIF0DATA0_NAME "gpio1b4_cif0data0_name" +#define GPIO1B3_CIF0CLKOUT_NAME "gpio1b3_cif0clkout_name" +#define GPIO1B2_SPDIFTX_NAME "gpio1b2_spdiftx_name" +#define GPIO1B1_UART2SOUT_NAME "gpio1b1_uart2sout_name" +#define GPIO1B0_UART2SIN_NAME "gpio1b0_uart2sin_name" //GPIO1C -#define GPIO1C7_CIFDATA9_RMIIRXD0_NAME "gpio1c7_cifdata9_rmiirxd0_name" -#define GPIO1C6_CIFDATA8_RMIIRXD1_NAME "gpio1c6_cifdata8_rmiirxd1_name" -#define GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME "gpio1c5_cifdata7_rmiicrsdvalid_name" -#define GPIO1C4_CIFDATA6_RMIIRXERR_NAME "gpio1c4_cifdata6_rmiirxerr_name" -#define GPIO1C3_CIFDATA5_RMIITXD0_NAME "gpio1c3_cifdata5_rmiitxd0_name" -#define GPIO1C2_CIF1DATA4_RMIITXD1_NAME "gpio1c2_cif1data4_rmiitxd1_name" -#define GPIO1C1_CIFDATA3_RMIITXEN_NAME "gpio1c1_cifdata3_rmiitxen_name" -#define GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME "gpio1c0_cif1data2_rmiiclkout_rmiiclkin_name" +#define GPIO1C7_CIFDATA9_RMIIRXD0_NAME "gpio1c7_cifdata9_rmiirxd0_name" +#define GPIO1C6_CIFDATA8_RMIIRXD1_NAME "gpio1c6_cifdata8_rmiirxd1_name" +#define GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME "gpio1c5_cifdata7_rmiicrsdvalid_name" +#define GPIO1C4_CIFDATA6_RMIIRXERR_NAME "gpio1c4_cifdata6_rmiirxerr_name" +#define GPIO1C3_CIFDATA5_RMIITXD0_NAME "gpio1c3_cifdata5_rmiitxd0_name" +#define GPIO1C2_CIF1DATA4_RMIITXD1_NAME "gpio1c2_cif1data4_rmiitxd1_name" +#define GPIO1C1_CIFDATA3_RMIITXEN_NAME "gpio1c1_cifdata3_rmiitxen_name" +#define GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME "gpio1c0_cif1data2_rmiiclkout_rmiiclkin_name" //GPIO1D -#define GPIO1D7_CIF1CLKOUT_NAME "gpio1d7_cif1clkout_name" -#define GPIO1D6_CIF1DATA11_NAME "gpio1d6_cif1data11_name" -#define GPIO1D5_CIF1DATA10_NAME "gpio1d5_cif1data10_name" -#define GPIO1D4_CIF1DATA1_NAME "gpio1d4_cif1data1_name" -#define GPIO1D3_CIF1DATA0_NAME "gpio1d3_cif1data0_name" -#define GPIO1D2_CIF1CLKIN_NAME "gpio1d2_cif1clkin_name" -#define GPIO1D1_CIF1HREF_MIIMDCLK_NAME "gpio1d1_cif1href_miimdclk_name" -#define GPIO1D0_CIF1VSYNC_MIIMD_NAME "gpio1d0_cif1vsync_miimd_name" +#define GPIO1D7_CIF1CLKOUT_NAME "gpio1d7_cif1clkout_name" +#define GPIO1D6_CIF1DATA11_NAME "gpio1d6_cif1data11_name" +#define GPIO1D5_CIF1DATA10_NAME "gpio1d5_cif1data10_name" +#define GPIO1D4_CIF1DATA1_NAME "gpio1d4_cif1data1_name" +#define GPIO1D3_CIF1DATA0_NAME "gpio1d3_cif1data0_name" +#define GPIO1D2_CIF1CLKIN_NAME "gpio1d2_cif1clkin_name" +#define GPIO1D1_CIF1HREF_MIIMDCLK_NAME "gpio1d1_cif1href_miimdclk_name" +#define GPIO1D0_CIF1VSYNC_MIIMD_NAME "gpio1d0_cif1vsync_miimd_name" //GPIO2A -#define GPIO2A7_LCDC1DATA7_SMCADDR11_NAME "gpio2a7_lcdc1data7_smcaddr11_name" -#define GPIO2A6_LCDC1DATA6_SMCADDR10_NAME "gpio2a6_lcdc1data6_smcaddr10_name" -#define GPIO2A5_LCDC1DATA5_SMCADDR9_NAME "gpio2a5_lcdc1data5_smcaddr9_name" -#define GPIO2A4_LCDC1DATA4_SMCADDR8_NAME "gpio2a4_lcdc1data4_smcaddr8_name" -#define GPIO2A3_LCDCDATA3_SMCADDR7_NAME "gpio2a3_lcdcdata3_smcaddr7_name" -#define GPIO2A2_LCDCDATA2_SMCADDR6_NAME "gpio2a2_lcdcdata2_smcaddr6_name" -#define GPIO2A1_LCDC1DATA1_SMCADDR5_NAME "gpio2a1_lcdc1data1_smcaddr5_name" -#define GPIO2A0_LCDC1DATA0_SMCADDR4_NAME "gpio2a0_lcdc1data0_smcaddr4_name" +#define GPIO2A7_LCDC1DATA7_SMCADDR11_NAME "gpio2a7_lcdc1data7_smcaddr11_name" +#define GPIO2A6_LCDC1DATA6_SMCADDR10_NAME "gpio2a6_lcdc1data6_smcaddr10_name" +#define GPIO2A5_LCDC1DATA5_SMCADDR9_NAME "gpio2a5_lcdc1data5_smcaddr9_name" +#define GPIO2A4_LCDC1DATA4_SMCADDR8_NAME "gpio2a4_lcdc1data4_smcaddr8_name" +#define GPIO2A3_LCDCDATA3_SMCADDR7_NAME "gpio2a3_lcdcdata3_smcaddr7_name" +#define GPIO2A2_LCDCDATA2_SMCADDR6_NAME "gpio2a2_lcdcdata2_smcaddr6_name" +#define GPIO2A1_LCDC1DATA1_SMCADDR5_NAME "gpio2a1_lcdc1data1_smcaddr5_name" +#define GPIO2A0_LCDC1DATA0_SMCADDR4_NAME "gpio2a0_lcdc1data0_smcaddr4_name" //GPIO2B #define GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME "gpio2b7_lcdc1data15_smcaddr19_hsadcdata7_name" -#define GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME "gpio2b6_lcdc1data14_smcaddr18_tssync_name" +#define GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME "gpio2b6_lcdc1data14_smcaddr18_tssync_name" #define GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME "gpio2b5_lcdc1data13_smcaddr17_hsadcdata8_name" #define GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME "gpio2b4_lcdc1data12_smcaddr16_hsadcdata9_name" -#define GPIO2B3_LCDC1DATA11_SMCADDR15_NAME "gpio2b3_lcdc1data11_smcaddr15_name" -#define GPIO2B2_LCDC1DATA10_SMCADDR14_NAME "gpio2b2_lcdc1data10_smcaddr14_name" -#define GPIO2B1_LCDC1DATA9_SMCADDR13_NAME "gpio2b1_lcdc1data9_smcaddr13_name" -#define GPIO2B0_LCDC1DATA8_SMCADDR12_NAME "gpio2b0_lcdc1data8_smcaddr12_name" +#define GPIO2B3_LCDC1DATA11_SMCADDR15_NAME "gpio2b3_lcdc1data11_smcaddr15_name" +#define GPIO2B2_LCDC1DATA10_SMCADDR14_NAME "gpio2b2_lcdc1data10_smcaddr14_name" +#define GPIO2B1_LCDC1DATA9_SMCADDR13_NAME "gpio2b1_lcdc1data9_smcaddr13_name" +#define GPIO2B0_LCDC1DATA8_SMCADDR12_NAME "gpio2b0_lcdc1data8_smcaddr12_name" //GPIO2C #define GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME "gpio2c7_lcdc1data23_spi1csn1_hsadcdata4_name" -#define GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME "gpio2c6_lcdc1data22_spi1rxd_hsadcdata3_name" -#define GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME "gpio2c5_lcdc1data21_spi1txd_hsadcdata2_name" +#define GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME "gpio2c6_lcdc1data22_spi1rxd_hsadcdata3_name" +#define GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME "gpio2c5_lcdc1data21_spi1txd_hsadcdata2_name" #define GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME "gpio2c4_lcdc1data20_spi1csn0_hsadcdata1_name" -#define GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME "gpio2c3_lcdc1data19_spi1clk_hsadcdata0_name" +#define GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME "gpio2c3_lcdc1data19_spi1clk_hsadcdata0_name" #define GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME "gpio2c2_lcdc1data18_smcblsn1_hsadcdata5_name" #define GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME "gpio2c1_lcdc1data17_smcblsn0_hsadcdata6_name" -#define GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME "gpio2c0_lcdcdata16_gpsclk_hsadcclkout_name" +#define GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME "gpio2c0_lcdcdata16_gpsclk_hsadcclkout_name" //GPIO2D -#define GPIO2D7_I2C1SCL_NAME "gpio2d7_i2c1scl_name" -#define GPIO2D6_I2C1SDA_NAME "gpio2d6_i2c1sda_name" -#define GPIO2D5_I2C0SCL_NAME "gpio2d5_i2c0scl_name" -#define GPIO2D4_I2C0SDA_NAME "gpio2d4_i2c0sda_name" -#define GPIO2D3_LCDC1VSYNC_NAME "gpio2d3_lcdc1vsync_name" -#define GPIO2D2_LCDC1HSYNC_NAME "gpio2d2_lcdc1hsync_name" -#define GPIO2D1_LCDC1DEN_SMCCSN1_NAME "gpio2d1_lcdc1den_smccsn1_name" -#define GPIO2D0_LCDC1DCLK_NAME "gpio2d0_lcdc1dclk_name" +#define GPIO2D7_I2C1SCL_NAME "gpio2d7_i2c1scl_name" +#define GPIO2D6_I2C1SDA_NAME "gpio2d6_i2c1sda_name" +#define GPIO2D5_I2C0SCL_NAME "gpio2d5_i2c0scl_name" +#define GPIO2D4_I2C0SDA_NAME "gpio2d4_i2c0sda_name" +#define GPIO2D3_LCDC1VSYNC_NAME "gpio2d3_lcdc1vsync_name" +#define GPIO2D2_LCDC1HSYNC_NAME "gpio2d2_lcdc1hsync_name" +#define GPIO2D1_LCDC1DEN_SMCCSN1_NAME "gpio2d1_lcdc1den_smccsn1_name" +#define GPIO2D0_LCDC1DCLK_NAME "gpio2d0_lcdc1dclk_name" //GPIO3A -#define GPIO3A7_SDMMC0WRITEPRT_NAME "gpio3a7_sdmmc0writeprt_name" -#define GPIO3A6_SDMMC0RSTNOUT_NAME "gpio3a6_sdmmc0rstnout_name" -#define GPIO4A5_I2C4SCL_NAME "gpio4a5_i2c4scl_name" -#define GPIO3A4_I2C4SDA_NAME "gpio3a4_i2c4sda_name" -#define GPIO3A3_I2C3SCL_NAME "gpio3a3_i2c3scl_name" -#define GPIO3A2_I2C3SDA_NAME "gpio3a2_i2c3sda_name" -#define GPIO3A1_I2C2SCL_NAME "gpio3a1_i2c2scl_name" -#define GPIO3A0_I2C2SDA_NAME "gpio3a0_i2c2sda_name" +#define GPIO3A7_SDMMC0WRITEPRT_NAME "gpio3a7_sdmmc0writeprt_name" +#define GPIO3A6_SDMMC0RSTNOUT_NAME "gpio3a6_sdmmc0rstnout_name" +#define GPIO4A5_I2C4SCL_NAME "gpio4a5_i2c4scl_name" +#define GPIO3A4_I2C4SDA_NAME "gpio3a4_i2c4sda_name" +#define GPIO3A3_I2C3SCL_NAME "gpio3a3_i2c3scl_name" +#define GPIO3A2_I2C3SDA_NAME "gpio3a2_i2c3sda_name" +#define GPIO3A1_I2C2SCL_NAME "gpio3a1_i2c2scl_name" +#define GPIO3A0_I2C2SDA_NAME "gpio3a0_i2c2sda_name" //GPIO3B -#define GPIO3B7_SDMMC0WRITEPRT_NAME "gpio3b7_sdmmc0writeprt_name" -#define GPIO3B6_SDMMC0DETECTN_NAME "gpio3b6_sdmmc0detectn_name" -#define GPIO3B5_SDMMC0DATA3_NAME "gpio3b5_sdmmc0data3_name" -#define GPIO3B4_SDMMC0DATA2_NAME "gpio3b4_sdmmc0data2_name" -#define GPIO3B3_SDMMC0DATA1_NAME "gpio3b3_sdmmc0data1_name" -#define GPIO3B2_SDMMC0DATA0_NAME "gpio3b2_sdmmc0data0_name" -#define GPIO3B1_SDMMC0CMD_NAME "gpio3b1_sdmmc0cmd_name" -#define GPIO3B0_SDMMC0CLKOUT_NAME "gpio3b0_sdmmc0clkout_name" +#define GPIO3B7_SDMMC0WRITEPRT_NAME "gpio3b7_sdmmc0writeprt_name" +#define GPIO3B6_SDMMC0DETECTN_NAME "gpio3b6_sdmmc0detectn_name" +#define GPIO3B5_SDMMC0DATA3_NAME "gpio3b5_sdmmc0data3_name" +#define GPIO3B4_SDMMC0DATA2_NAME "gpio3b4_sdmmc0data2_name" +#define GPIO3B3_SDMMC0DATA1_NAME "gpio3b3_sdmmc0data1_name" +#define GPIO3B2_SDMMC0DATA0_NAME "gpio3b2_sdmmc0data0_name" +#define GPIO3B1_SDMMC0CMD_NAME "gpio3b1_sdmmc0cmd_name" +#define GPIO3B0_SDMMC0CLKOUT_NAME "gpio3b0_sdmmc0clkout_name" //GPIO3C -#define GPIO3C7_SDMMC1WRITEPRT_NAME "gpio3c7_sdmmc1writeprt_name" -#define GPIO3C6_SDMMC1DETECTN_NAME "gpio3c6_sdmmc1detectn_name" -#define GPIO3C5_SDMMC1CLKOUT_NAME "gpio3c5_sdmmc1clkout_name" -#define GPIO3C4_SDMMC1DATA3_NAME "gpio3c4_sdmmc1data3_name" -#define GPIO3C3_SDMMC1DATA2_NAME "gpio3c3_sdmmc1data2_name" -#define GPIO3C2_SDMMC1DATA1_NAME "gpio3c2_sdmmc1data1_name" -#define GPIO3C1_SDMMC1DATA0_NAME "gpio3c1_sdmmc1data0_name" -#define GPIO3C0_SMMC1CMD_NAME "gpio3c0_smmc1cmd_name" +#define GPIO3C7_SDMMC1WRITEPRT_NAME "gpio3c7_sdmmc1writeprt_name" +#define GPIO3C6_SDMMC1DETECTN_NAME "gpio3c6_sdmmc1detectn_name" +#define GPIO3C5_SDMMC1CLKOUT_NAME "gpio3c5_sdmmc1clkout_name" +#define GPIO3C4_SDMMC1DATA3_NAME "gpio3c4_sdmmc1data3_name" +#define GPIO3C3_SDMMC1DATA2_NAME "gpio3c3_sdmmc1data2_name" +#define GPIO3C2_SDMMC1DATA1_NAME "gpio3c2_sdmmc1data1_name" +#define GPIO3C1_SDMMC1DATA0_NAME "gpio3c1_sdmmc1data0_name" +#define GPIO3C0_SMMC1CMD_NAME "gpio3c0_smmc1cmd_name" //GPIO3D -#define GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME "gpio3d7_flashdqs_emmcclkout_name" -#define GPIO3D6_UART3RTSN_NAME "gpio3d6_uart3rtsn_name" -#define GPIO3D5_UART3CTSN_NAME "gpio3d5_uart3ctsn_name" -#define GPIO3D4_UART3SOUT_NAME "gpio3d4_uart3sout_name" -#define GPIO3D3_UART3SIN_NAME "gpio3d3_uart3sin_name" -#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name" -#define GPIO3D1_SDMMC1BACKENDPWR_NAME "gpio3d1_sdmmc1backendpwr_name" -#define GPIO3D0_SDMMC1PWREN_NAME "gpio3d0_sdmmc1pwren_name" +#define GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME "gpio3d7_flashdqs_emmcclkout_name" +#define GPIO3D6_UART3RTSN_NAME "gpio3d6_uart3rtsn_name" +#define GPIO3D5_UART3CTSN_NAME "gpio3d5_uart3ctsn_name" +#define GPIO3D4_UART3SOUT_NAME "gpio3d4_uart3sout_name" +#define GPIO3D3_UART3SIN_NAME "gpio3d3_uart3sin_name" +#define GPIO3D2_SDMMC1INTN_NAME "gpio3d2_sdmmc1intn_name" +#define GPIO3D1_SDMMC1BACKENDPWR_NAME "gpio3d1_sdmmc1backendpwr_name" +#define GPIO3D0_SDMMC1PWREN_NAME "gpio3d0_sdmmc1pwren_name" //GPIO4A -#define GPIO4A7_FLASHDATA15_NAME "gpio4a7_flashdata15_name" -#define GPIO4A6_FLASHDATA14_NAME "gpio4a6_flashdata14_name" -#define GPIO4A5_FLASHDATA13_NAME "gpio4a5_flashdata13_name" -#define GPIO4A4_FLASHDATA12_NAME "gpio4a4_flashdata12_name" -#define GPIO4A3_FLASHDATA11_NAME "gpio4a3_flashdata11_name" -#define GPIO4A2_FLASHDATA10_NAME "gpio4a2_flashdata10_name" -#define GPIO4A1_FLASHDATA9_NAME "gpio4a1_flashdata9_name" -#define GPIO4A0_FLASHDATA8_NAME "gpio4a0_flashdata8_name" +#define GPIO4A7_FLASHDATA15_NAME "gpio4a7_flashdata15_name" +#define GPIO4A6_FLASHDATA14_NAME "gpio4a6_flashdata14_name" +#define GPIO4A5_FLASHDATA13_NAME "gpio4a5_flashdata13_name" +#define GPIO4A4_FLASHDATA12_NAME "gpio4a4_flashdata12_name" +#define GPIO4A3_FLASHDATA11_NAME "gpio4a3_flashdata11_name" +#define GPIO4A2_FLASHDATA10_NAME "gpio4a2_flashdata10_name" +#define GPIO4A1_FLASHDATA9_NAME "gpio4a1_flashdata9_name" +#define GPIO4A0_FLASHDATA8_NAME "gpio4a0_flashdata8_name" //GPIO4B -#define GPIO4B7_SPI0CSN1_NAME "gpio4b7_spi0csn1_name" -#define GPIO4B6_FLASHCSN7_NAME "gpio4b6_flashcsn7_name" -#define GPIO4B5_FLASHCSN6_NAME "gpio4b5_flashcsn6_name" -#define GPIO4B4_FLASHCSN5_NAME "gpio4b4_flashcsn5_name" -#define GPIO4B3_FLASHCSN4_NAME "gpio4b3_flashcsn4_name" -#define GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME "gpio4b2_flashcsn3_emmcrstnout_name" -#define GPIO4B1_FLASHCSN2_EMMCCMD_NAME "gpio4b1_flashcsn2_emmccmd_name" -#define GPIO4B0_FLASHCSN1_NAME "gpio4b0_flashcsn1_name" +#define GPIO4B7_SPI0CSN1_NAME "gpio4b7_spi0csn1_name" +#define GPIO4B6_FLASHCSN7_NAME "gpio4b6_flashcsn7_name" +#define GPIO4B5_FLASHCSN6_NAME "gpio4b5_flashcsn6_name" +#define GPIO4B4_FLASHCSN5_NAME "gpio4b4_flashcsn5_name" +#define GPIO4B3_FLASHCSN4_NAME "gpio4b3_flashcsn4_name" +#define GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME "gpio4b2_flashcsn3_emmcrstnout_name" +#define GPIO4B1_FLASHCSN2_EMMCCMD_NAME "gpio4b1_flashcsn2_emmccmd_name" +#define GPIO4B0_FLASHCSN1_NAME "gpio4b0_flashcsn1_name" //GPIO4C -#define GPIO4C7_SMCDATA7_TRACEDATA7_NAME "gpio4c7_smcdata7_tracedata7_name" -#define GPIO4C6_SMCDATA6_TRACEDATA6_NAME "gpio4c6_smcdata6_tracedata6_name" -#define GPIO4C5_SMCDATA5_TRACEDATA5_NAME "gpio4c5_smcdata5_tracedata5_name" -#define GPIO4C4_SMCDATA4_TRACEDATA4_NAME "gpio4c4_smcdata4_tracedata4_name" -#define GPIO4C3_SMCDATA3_TRACEDATA3_NAME "gpio4c3_smcdata3_tracedata3_name" -#define GPIO4C2_SMCDATA2_TRACEDATA2_NAME "gpio4c2_smcdata2_tracedata2_name" -#define GPIO4C1_SMCDATA1_TRACEDATA1_NAME "gpio4c1_smcdata1_tracedata1_name" -#define GPIO4C0_SMCDATA0_TRACEDATA0_NAME "gpio4c0_smcdata0_tracedata0_name" +#define GPIO4C7_SMCDATA7_TRACEDATA7_NAME "gpio4c7_smcdata7_tracedata7_name" +#define GPIO4C6_SMCDATA6_TRACEDATA6_NAME "gpio4c6_smcdata6_tracedata6_name" +#define GPIO4C5_SMCDATA5_TRACEDATA5_NAME "gpio4c5_smcdata5_tracedata5_name" +#define GPIO4C4_SMCDATA4_TRACEDATA4_NAME "gpio4c4_smcdata4_tracedata4_name" +#define GPIO4C3_SMCDATA3_TRACEDATA3_NAME "gpio4c3_smcdata3_tracedata3_name" +#define GPIO4C2_SMCDATA2_TRACEDATA2_NAME "gpio4c2_smcdata2_tracedata2_name" +#define GPIO4C1_SMCDATA1_TRACEDATA1_NAME "gpio4c1_smcdata1_tracedata1_name" +#define GPIO4C0_SMCDATA0_TRACEDATA0_NAME "gpio4c0_smcdata0_tracedata0_name" //GPIO4D -#define GPIO4D7_SMCDATA15_TRACEDATA15_NAME "gpio4d7_smcdata15_tracedata15_name" -#define GPIO4D6_SMCDATA14_TRACEDATA14_NAME "gpio4d6_smcdata14_tracedata14_name" -#define GPIO4D5_SMCDATA13_TRACEDATA13_NAME "gpio4d5_smcdata13_tracedata13_name" -#define GPIO4D4_SMCDATA12_TRACEDATA12_NAME "gpio4d4_smcdata12_tracedata12_name" -#define GPIO4D3_SMCDATA11_TRACEDATA11_NAME "gpio4d3_smcdata11_tracedata11_name" -#define GPIO4D2_SMCDATA10_TRACEDATA10_NAME "gpio4d2_smcdata10_tracedata10_name" -#define GPIO4D1_SMCDATA9_TRACEDATA9_NAME "gpio4d1_smcdata9_tracedata9_name" -#define GPIO4D0_SMCDATA8_TRACEDATA8_NAME "gpio4d0_smcdata8_tracedata8_name" +#define GPIO4D7_SMCDATA15_TRACEDATA15_NAME "gpio4d7_smcdata15_tracedata15_name" +#define GPIO4D6_SMCDATA14_TRACEDATA14_NAME "gpio4d6_smcdata14_tracedata14_name" +#define GPIO4D5_SMCDATA13_TRACEDATA13_NAME "gpio4d5_smcdata13_tracedata13_name" +#define GPIO4D4_SMCDATA12_TRACEDATA12_NAME "gpio4d4_smcdata12_tracedata12_name" +#define GPIO4D3_SMCDATA11_TRACEDATA11_NAME "gpio4d3_smcdata11_tracedata11_name" +#define GPIO4D2_SMCDATA10_TRACEDATA10_NAME "gpio4d2_smcdata10_tracedata10_name" +#define GPIO4D1_SMCDATA9_TRACEDATA9_NAME "gpio4d1_smcdata9_tracedata9_name" +#define GPIO4D0_SMCDATA8_TRACEDATA8_NAME "gpio4d0_smcdata8_tracedata8_name" //GPIO6B -#define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name" +#define GPIO6B7_TESTCLOCKOUT_NAME "gpio6b7_testclockout_name" #define MUX_CFG(desc,reg,off,interl,mux_mode,bflags) \ { \ diff --git a/arch/arm/mach-rk30/iomux.c b/arch/arm/mach-rk30/iomux.c index 231d4ca2c37c..daa3aafdcf17 100755 --- a/arch/arm/mach-rk30/iomux.c +++ b/arch/arm/mach-rk30/iomux.c @@ -30,104 +30,104 @@ static struct mux_config rk30_muxs[] = { * reg offset inter mode */ //GPIO0A -MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO0A7_I2S8CHSDI_NAME, GPIO0A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO0A4_PWM1_NAME, GPIO0A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO0A3_PWM0_NAME, GPIO0A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO0A2_HDMII2CSDA_NAME, GPIO0A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO0A1_HDMII2CSCL_NAME, GPIO0A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO0A0_HDMIHOTPLUGIN_NAME, GPIO0A, 0, 2, 0, DEFAULT) //GPIO0B -MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO0B7_I2S8CHSDO3_NAME, GPIO0B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO0B6_I2S8CHSDO2_NAME, GPIO0B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO0B5_I2S8CHSDO1_NAME, GPIO0B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO0B4_I2S8CHSDO0_NAME, GPIO0B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO0B3_I2S8CHLRCKTX_NAME, GPIO0B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO0B2_I2S8CHLRCKRX_NAME, GPIO0B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO0B1_I2S8CHSCLK_NAME, GPIO0B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO0B0_I2S8CHCLK_NAME, GPIO0B, 0, 2, 0, DEFAULT) //GPIO0C -MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO0C6_TRACECLK_SMCADDR2_NAME, GPIO0C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO0C2_I2S8CHLRCKRX_NAME, GPIO0C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO0C7_TRACECTL_SMCADDR3_NAME, GPIO0C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO0C6_TRACECLK_SMCADDR2_NAME, GPIO0C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO0C5_I2S12CHSDO_NAME, GPIO0C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO0C4_I2S12CHSDI_NAME, GPIO0C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO0C3_I2S12CHLRCKTX_NAME, GPIO0C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO0C2_I2S8CHLRCKRX_NAME, GPIO0C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO0C1_I2S12CHSCLK_NAME, GPIO0C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO0C0_I2S12CHCLK_NAME, GPIO0C, 0, 2, 0, DEFAULT) //GPIO0D -MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO0D4_I2S12CHSDI_SMCADDR0_NAME, GPIO0D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO0D3_I2S12CHLRCKTX_SMCADVN_NAME, GPIO0D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO0D2_I2S12CHLRCKRX_SMCOEN_NAME, GPIO0D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME, GPIO0D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO0D7_PWM3_NAME, GPIO0D, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO0D6_PWM2_NAME, GPIO0D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME, GPIO0D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO0D4_I2S12CHSDI_SMCADDR0_NAME, GPIO0D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO0D3_I2S12CHLRCKTX_SMCADVN_NAME, GPIO0D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO0D2_I2S12CHLRCKRX_SMCOEN_NAME, GPIO0D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME, GPIO0D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D, 0, 2, 0, DEFAULT) //GPIO1A -MUX_CFG(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO1A7_UART1RTSN_SPI0TXD_NAME, GPIO1A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO1A6_UART1CTSN_SPI0RXD_NAME, GPIO1A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1A5_UART1SOUT_SPI0CLK_NAME, GPIO1A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1A4_UART1SIN_SPI0CSN0_NAME, GPIO1A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1A3_UART0RTSN_NAME, GPIO1A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO1A2_UART0CTSN_NAME, GPIO1A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO1A1_UART0SOUT_NAME, GPIO1A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO1A0_UART0SIN_NAME, GPIO1A, 0, 2, 0, DEFAULT) //GPIO1B -MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO1B7_CIFDATA11_NAME, GPIO1B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO1B6_CIFDATA10_NAME, GPIO1B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1B5_CIF0DATA1_NAME, GPIO1B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1B4_CIF0DATA0_NAME, GPIO1B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1B3_CIF0CLKOUT_NAME, GPIO1B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO1B2_SPDIFTX_NAME, GPIO1B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO1B1_UART2SOUT_NAME, GPIO1B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO1B0_UART2SIN_NAME, GPIO1B, 0, 2, 0, DEFAULT) //GPIO1C -MUX_CFG(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO1C7_CIFDATA9_RMIIRXD0_NAME, GPIO1C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO1C6_CIFDATA8_RMIIRXD1_NAME, GPIO1C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME, GPIO1C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1C4_CIFDATA6_RMIIRXERR_NAME, GPIO1C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1C3_CIFDATA5_RMIITXD0_NAME, GPIO1C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO1C2_CIF1DATA4_RMIITXD1_NAME, GPIO1C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO1C1_CIFDATA3_RMIITXEN_NAME, GPIO1C, 2, 2, 0, DEFAULT) MUX_CFG(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME, GPIO1C, 0, 2, 0, DEFAULT) //GPIO1D -MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO1D7_CIF1CLKOUT_NAME, GPIO1D, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO1D6_CIF1DATA11_NAME, GPIO1D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO1D5_CIF1DATA10_NAME, GPIO1D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO1D4_CIF1DATA1_NAME, GPIO1D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO1D3_CIF1DATA0_NAME, GPIO1D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO1D2_CIF1CLKIN_NAME, GPIO1D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO1D1_CIF1HREF_MIIMDCLK_NAME, GPIO1D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO1D0_CIF1VSYNC_MIIMD_NAME, GPIO1D, 0, 2, 0, DEFAULT) //GPIO2A -MUX_CFG(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME, GPIO2A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME, GPIO2A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME, GPIO2A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME, GPIO2A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2A3_LCDCDATA3_SMCADDR7_NAME, GPIO2A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME, GPIO2A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME, GPIO2A, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME, GPIO2A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME, GPIO2A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME, GPIO2A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME, GPIO2A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO2A3_LCDCDATA3_SMCADDR7_NAME, GPIO2A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2A2_LCDCDATA2_SMCADDR6_NAME, GPIO2A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME, GPIO2A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME, GPIO2A, 0, 2, 0, DEFAULT) //GPIO2B MUX_CFG(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME, GPIO2B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME, GPIO2B, 12, 2, 0, DEFAULT) MUX_CFG(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME, GPIO2B, 10, 2, 0, DEFAULT) MUX_CFG(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME, GPIO2B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME, GPIO2B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME, GPIO2B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME, GPIO2B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME, GPIO2B, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME, GPIO2B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME, GPIO2B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME, GPIO2B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME, GPIO2B, 0, 2, 0, DEFAULT) //GPIO2C MUX_CFG(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME, GPIO2C, 14, 2, 0, DEFAULT) @@ -140,97 +140,97 @@ MUX_CFG(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME, GPIO2C, 2, 2, 0, DEFA MUX_CFG(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME, GPIO2C, 0, 2, 0, DEFAULT) //GPIO2D -MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO2D1_LCDC1DEN_SMCCSN1_NAME, GPIO2D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO2D7_I2C1SCL_NAME, GPIO2D, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO2D6_I2C1SDA_NAME, GPIO2D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO2D5_I2C0SCL_NAME, GPIO2D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO2D4_I2C0SDA_NAME, GPIO2D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO2D3_LCDC1VSYNC_NAME, GPIO2D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO2D2_LCDC1HSYNC_NAME, GPIO2D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO2D1_LCDC1DEN_SMCCSN1_NAME, GPIO2D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO2D0_LCDC1DCLK_NAME, GPIO2D, 0, 2, 0, DEFAULT) //GPIO3A -MUX_CFG(GPIO3A7_SDMMC0WRITEPRT_NAME, GPIO3A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO4A5_I2C4SCL_NAME, GPIO3A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO3A7_SDMMC0WRITEPRT_NAME, GPIO3A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3A6_SDMMC0RSTNOUT_NAME, GPIO3A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO4A5_I2C4SCL_NAME, GPIO3A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3A4_I2C4SDA_NAME, GPIO3A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3A3_I2C3SCL_NAME, GPIO3A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO3A2_I2C3SDA_NAME, GPIO3A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO3A1_I2C2SCL_NAME, GPIO3A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3A0_I2C2SDA_NAME, GPIO3A, 0, 2, 0, DEFAULT) //GPIO3B -MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO3B7_SDMMC0WRITEPRT_NAME, GPIO3B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3B6_SDMMC0DETECTN_NAME, GPIO3B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3B5_SDMMC0DATA3_NAME, GPIO3B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3B4_SDMMC0DATA2_NAME, GPIO3B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3B3_SDMMC0DATA1_NAME, GPIO3B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO3B2_SDMMC0DATA0_NAME, GPIO3B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO3B1_SDMMC0CMD_NAME, GPIO3B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3B0_SDMMC0CLKOUT_NAME, GPIO3B, 0, 2, 0, DEFAULT) //GPIO3C -MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO3C7_SDMMC1WRITEPRT_NAME, GPIO3C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3C6_SDMMC1DETECTN_NAME, GPIO3C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3C5_SDMMC1CLKOUT_NAME, GPIO3C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3C4_SDMMC1DATA3_NAME, GPIO3C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3C3_SDMMC1DATA2_NAME, GPIO3C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO3C2_SDMMC1DATA1_NAME, GPIO3C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO3C1_SDMMC1DATA0_NAME, GPIO3C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3C0_SMMC1CMD_NAME, GPIO3C, 0, 2, 0, DEFAULT) //GPIO3D -MUX_CFG(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME, GPIO3D, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME, GPIO3D, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO3D6_UART3RTSN_NAME, GPIO3D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO3D5_UART3CTSN_NAME, GPIO3D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO3D4_UART3SOUT_NAME, GPIO3D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO3D3_UART3SIN_NAME, GPIO3D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO3D2_SDMMC1INTN_NAME, GPIO3D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO3D1_SDMMC1BACKENDPWR_NAME, GPIO3D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO3D0_SDMMC1PWREN_NAME, GPIO3D, 0, 2, 0, DEFAULT) //GPIO4A -MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO4A7_FLASHDATA15_NAME, GPIO4A, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO4A6_FLASHDATA14_NAME, GPIO4A, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO4A5_FLASHDATA13_NAME, GPIO4A, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO4A4_FLASHDATA12_NAME, GPIO4A, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO4A3_FLASHDATA11_NAME, GPIO4A, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO4A2_FLASHDATA10_NAME, GPIO4A, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO4A1_FLASHDATA9_NAME, GPIO4A, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO4A0_FLASHDATA8_NAME, GPIO4A, 0, 2, 0, DEFAULT) //GPIO4B -MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO4B, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO4B1_FLASHCSN2_EMMCCMD_NAME, GPIO4B, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO4B7_SPI0CSN1_NAME, GPIO4B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO4B6_FLASHCSN7_NAME, GPIO4B, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO4B5_FLASHCSN6_NAME, GPIO4B, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO4B4_FLASHCSN5_NAME, GPIO4B, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO4B3_FLASHCSN4_NAME, GPIO4B, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME, GPIO4B, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO4B1_FLASHCSN2_EMMCCMD_NAME, GPIO4B, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO4B0_FLASHCSN1_NAME, GPIO4B, 0, 2, 0, DEFAULT) //GPIO4C -MUX_CFG(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO4C5_SMCDATA5_TRACEDATA5_NAME, GPIO4C, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO4C1_SMCDATA1_TRACEDATA1_NAME, GPIO4C, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO4C7_SMCDATA7_TRACEDATA7_NAME, GPIO4C, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO4C6_SMCDATA6_TRACEDATA6_NAME, GPIO4C, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO4C5_SMCDATA5_TRACEDATA5_NAME, GPIO4C, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO4C4_SMCDATA4_TRACEDATA4_NAME, GPIO4C, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO4C3_SMCDATA3_TRACEDATA3_NAME, GPIO4C, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO4C2_SMCDATA2_TRACEDATA2_NAME, GPIO4C, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO4C1_SMCDATA1_TRACEDATA1_NAME, GPIO4C, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO4C0_SMCDATA0_TRACEDATA0_NAME, GPIO4C, 0, 2, 0, DEFAULT) //GPIO4D -MUX_CFG(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D, 14, 2, 0, DEFAULT) -MUX_CFG(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D, 12, 2, 0, DEFAULT) -MUX_CFG(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D, 10, 2, 0, DEFAULT) -MUX_CFG(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D, 8, 2, 0, DEFAULT) -MUX_CFG(GPIO4D3_SMCDATA11_TRACEDATA11_NAME, GPIO4D, 6, 2, 0, DEFAULT) -MUX_CFG(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D, 4, 2, 0, DEFAULT) -MUX_CFG(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D, 2, 2, 0, DEFAULT) -MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT) +MUX_CFG(GPIO4D7_SMCDATA15_TRACEDATA15_NAME, GPIO4D, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO4D6_SMCDATA14_TRACEDATA14_NAME, GPIO4D, 12, 2, 0, DEFAULT) +MUX_CFG(GPIO4D5_SMCDATA13_TRACEDATA13_NAME, GPIO4D, 10, 2, 0, DEFAULT) +MUX_CFG(GPIO4D4_SMCDATA12_TRACEDATA12_NAME, GPIO4D, 8, 2, 0, DEFAULT) +MUX_CFG(GPIO4D3_SMCDATA11_TRACEDATA11_NAME, GPIO4D, 6, 2, 0, DEFAULT) +MUX_CFG(GPIO4D2_SMCDATA10_TRACEDATA10_NAME, GPIO4D, 4, 2, 0, DEFAULT) +MUX_CFG(GPIO4D1_SMCDATA9_TRACEDATA9_NAME, GPIO4D, 2, 2, 0, DEFAULT) +MUX_CFG(GPIO4D0_SMCDATA8_TRACEDATA8_NAME, GPIO4D, 0, 2, 0, DEFAULT) //GPIO6B -MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 2, 0, DEFAULT) +MUX_CFG(GPIO6B7_TESTCLOCKOUT_NAME, GPIO6B, 14, 2, 0, DEFAULT) }; -- 2.34.1