From b573f99ab71413c718086eed89490635d52c685c Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 13:31:28 +0000
Subject: [PATCH] Add xor reg-reg pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SystemZ/SystemZInstrInfo.td | 7 +++++++
 test/CodeGen/SystemZ/02-RetXor.ll      | 6 ++++++
 test/CodeGen/SystemZ/02-RetXorImm.ll   | 6 ++++++
 3 files changed, 19 insertions(+)
 create mode 100644 test/CodeGen/SystemZ/02-RetXor.ll
 create mode 100644 test/CodeGen/SystemZ/02-RetXorImm.ll

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 66b2db972cb..c4121fe604f 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -77,5 +77,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 }
 // FIXME: provide patterns for masked or-with-imm
 
+let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
+// FIXME: Provide proper encoding!
+def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
+                     "xgr\t{$dst, $src2}",
+                     [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
+}
+
 } // Defs = [PSW]
 } // isTwoAddress = 1
diff --git a/test/CodeGen/SystemZ/02-RetXor.ll b/test/CodeGen/SystemZ/02-RetXor.ll
new file mode 100644
index 00000000000..b15d9460a60
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXor.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = xor i64 %a, %b
+    ret i64 %c
+}
\ No newline at end of file
diff --git a/test/CodeGen/SystemZ/02-RetXorImm.ll b/test/CodeGen/SystemZ/02-RetXorImm.ll
new file mode 100644
index 00000000000..f1f835a0edc
--- /dev/null
+++ b/test/CodeGen/SystemZ/02-RetXorImm.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc
+define i64 @foo(i64 %a, i64 %b) {
+entry:
+    %c = xor i64 %a, 1
+    ret i64 %c
+}
\ No newline at end of file
-- 
2.34.1