From b5902ed695ce372a13a993dd160f7ec2607b1e4d Mon Sep 17 00:00:00 2001 From: zsq Date: Wed, 29 Feb 2012 23:40:35 -0800 Subject: [PATCH] modify for rga.h independ --- drivers/video/rockchip/rga/RGA_API.c | 39 +++--- drivers/video/rockchip/rga/rga.h | 192 +++++++++++---------------- drivers/video/rockchip/rga/rga_drv.c | 26 +++- 3 files changed, 122 insertions(+), 135 deletions(-) diff --git a/drivers/video/rockchip/rga/RGA_API.c b/drivers/video/rockchip/rga/RGA_API.c index f7e7d0b0dd6e..7c3b4be9d7b3 100755 --- a/drivers/video/rockchip/rga/RGA_API.c +++ b/drivers/video/rockchip/rga/RGA_API.c @@ -83,10 +83,10 @@ matrix_cal(const struct rga_req *msg, TILE_INFO *tile) u32 RGA_dst_act_addr_temp(const struct rga_req *msg) { - u32 pw; - u32 x_off, y_off; - u32 stride; - u32 p; + uint32_t pw; + uint32_t x_off, y_off; + uint32_t stride; + uint32_t p; pw = RGA_pixel_width_init(msg->dst.format); stride = (msg->dst.vir_w * pw + 3) & (~3); @@ -100,11 +100,10 @@ RGA_dst_act_addr_temp(const struct rga_req *msg) } void -RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr) +RGA_set_cmd_info(uint8_t cmd_mode, uint32_t cmd_addr) { - u32 reg = 0; + uint32_t reg = 0; - //reg = rRGA_SYS_CTRL; reg |= ((cmd_mode & 1) << 1); rRGA_SYS_CTRL = reg; rRGA_CMD_ADDR = cmd_addr; @@ -113,8 +112,8 @@ RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr) void RGA_start(void) { - u32 reg = 0; - u8 cmd_mode; + uint32_t reg = 0; + uint8_t cmd_mode; reg = rRGA_SYS_CTRL; cmd_mode = (reg >> 2) & 1; @@ -138,7 +137,7 @@ RGA_start(void) void RGA_soft_reset(void) { - u32 reg = 0; + uint32_t reg = 0; reg = rRGA_SYS_CTRL; reg |= 1; @@ -185,7 +184,7 @@ void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info) } #endif -void rga_start_cmd_AXI(u8 *base, u32 num) +void rga_start_cmd_AXI(uint8_t *base, uint32_t num) { rRGA_SYS_CTRL = 0x4; rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE); @@ -196,8 +195,8 @@ void rga_start_cmd_AXI(u8 *base, u32 num) void rga_check_cmd_finish(void) { - u8 int_flag; - u8 error_flag; + uint8_t int_flag; + uint8_t error_flag; int_flag = 0; error_flag = 0; @@ -222,9 +221,9 @@ void rga_check_cmd_finish(void) -void rga_start_cmd_AHB(u8 *base) +void rga_start_cmd_AHB(uint8_t *base) { - u32 *base_p32; + uint32_t *base_p32; base_p32 = (u32 *)base; *base_p32 = (*base_p32 | (1<<29)); @@ -237,7 +236,7 @@ void rga_start_cmd_AHB(u8 *base) void rga_check_cmd_AHB_finish(void) { - u8 int_flag; + uint8_t int_flag; int_flag = 0; while(!int_flag) @@ -253,11 +252,11 @@ uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1) { struct rga_req *mp; - u32 w_ratio, h_ratio; - u32 stride; + uint32_t w_ratio, h_ratio; + uint32_t stride; - u32 daw, dah; - u32 pl; + uint32_t daw, dah; + uint32_t pl; daw = dah = 0; diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h index 90a17bf20d36..6a82646c11d4 100755 --- a/drivers/video/rockchip/rga/rga.h +++ b/drivers/video/rockchip/rga/rga.h @@ -1,11 +1,6 @@ #ifndef _RGA_DRIVER_H_ #define _RGA_DRIVER_H_ -#include "rga_type.h" -#include -#include -#include - #define RGA_BLIT_SYNC 0x5017 #define RGA_BLIT_ASYNC 0x5018 @@ -118,31 +113,31 @@ enum typedef struct rga_img_info_t { - uint32 yrgb_addr; /* yrgb mem addr */ - uint32 uv_addr; /* cb/cr mem addr */ - uint32 v_addr; /* cr mem addr */ - uint32 format; //definition by RK_FORMAT + unsigned int yrgb_addr; /* yrgb mem addr */ + unsigned int uv_addr; /* cb/cr mem addr */ + unsigned int v_addr; /* cr mem addr */ + unsigned int format; //definition by RK_FORMAT - UWORD16 act_w; - UWORD16 act_h; - UWORD16 x_offset; - UWORD16 y_offset; + unsigned short act_w; + unsigned short act_h; + unsigned short x_offset; + unsigned short y_offset; - UWORD16 vir_w; - UWORD16 vir_h; + unsigned short vir_w; + unsigned short vir_h; - UWORD16 endian_mode; //for BPP - UWORD16 alpha_swap; + unsigned short endian_mode; //for BPP + unsigned short alpha_swap; } rga_img_info_t; typedef struct mdp_img_act { - UWORD16 w; // width - UWORD16 h; // height - WORD16 x_off; // x offset for the vir - WORD16 y_off; // y offset for the vir + unsigned short w; // width + unsigned short h; // height + short x_off; // x offset for the vir + short y_off; // y offset for the vir } mdp_img_act; @@ -150,24 +145,24 @@ mdp_img_act; typedef struct RANGE { - UWORD16 min; - UWORD16 max; + unsigned short min; + unsigned short max; } RANGE; typedef struct POINT { - UWORD16 x; - UWORD16 y; + unsigned short x; + unsigned short y; } POINT; typedef struct RECT { - WORD16 xmin; - WORD16 xmax; // width - 1 - WORD16 ymin; - WORD16 ymax; // height - 1 + unsigned short xmin; + unsigned short xmax; // width - 1 + unsigned short ymin; + unsigned short ymax; // height - 1 } RECT; typedef struct RGB @@ -182,8 +177,8 @@ typedef struct RGB typedef struct MMU { unsigned char mmu_en; - uint32 base_addr; - uint32 mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ + uint32_t base_addr; + uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ } MMU; @@ -206,94 +201,94 @@ COLOR_FILL; typedef struct FADING { - UBYTE b; - UBYTE g; - UBYTE r; - UBYTE res; + uint8_t b; + uint8_t g; + uint8_t r; + uint8_t res; } FADING; typedef struct line_draw_t { - POINT start_point; /* LineDraw_start_point */ - POINT end_point; /* LineDraw_end_point */ - uint32 color; /* LineDraw_color */ - uint32 flag; /* (enum) LineDrawing mode sel */ - uint32 line_width; /* range 1~16 */ + POINT start_point; /* LineDraw_start_point */ + POINT end_point; /* LineDraw_end_point */ + uint32_t color; /* LineDraw_color */ + uint32_t flag; /* (enum) LineDrawing mode sel */ + uint32_t line_width; /* range 1~16 */ } line_draw_t; struct rga_req { - UBYTE render_mode; /* (enum) process mode sel */ + uint8_t render_mode; /* (enum) process mode sel */ - rga_img_info_t src; /* src image info */ - rga_img_info_t dst; /* dst image info */ - rga_img_info_t pat; /* patten image info */ + rga_img_info_t src; /* src image info */ + rga_img_info_t dst; /* dst image info */ + rga_img_info_t pat; /* patten image info */ - uint32 rop_mask_addr; /* rop4 mask addr */ - uint32 LUT_addr; /* LUT addr */ + uint32_t rop_mask_addr; /* rop4 mask addr */ + uint32_t LUT_addr; /* LUT addr */ - RECT clip; /* dst clip window default value is dst_vir */ - /* value from [0, w-1] / [0, h-1]*/ + RECT clip; /* dst clip window default value is dst_vir */ + /* value from [0, w-1] / [0, h-1]*/ - int32_t sina; /* dst angle default value 0 16.16 scan from table */ - int32_t cosa; /* dst angle default value 0 16.16 scan from table */ - - uint16_t alpha_rop_flag; /* alpha rop process flag */ - /* ([0] = 1 alpha_rop_enable) */ - /* ([1] = 1 rop enable) */ - /* ([2] = 1 fading_enable) */ - /* ([3] = 1 PD_enable) */ - /* ([4] = 1 alpha cal_mode_sel) */ - /* ([5] = 1 dither_enable) */ - /* ([6] = 1 gradient fill mode sel) */ - /* ([7] = 1 AA_enable) */ - - uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ + int32_t sina; /* dst angle default value 0 16.16 scan from table */ + int32_t cosa; /* dst angle default value 0 16.16 scan from table */ + + uint16_t alpha_rop_flag; /* alpha rop process flag */ + /* ([0] = 1 alpha_rop_enable) */ + /* ([1] = 1 rop enable) */ + /* ([2] = 1 fading_enable) */ + /* ([3] = 1 PD_enable) */ + /* ([4] = 1 alpha cal_mode_sel) */ + /* ([5] = 1 dither_enable) */ + /* ([6] = 1 gradient fill mode sel) */ + /* ([7] = 1 AA_enable) */ + + uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ - uint32 color_key_max; /* color key max */ - uint32 color_key_min; /* color key min */ + uint32_t color_key_max; /* color key max */ + uint32_t color_key_min; /* color key min */ - uint32 fg_color; /* foreground color */ - uint32 bg_color; /* background color */ + uint32_t fg_color; /* foreground color */ + uint32_t bg_color; /* background color */ - COLOR_FILL gr_color; /* color fill use gradient */ + COLOR_FILL gr_color; /* color fill use gradient */ line_draw_t line_draw_info; FADING fading; - uint8_t PD_mode; /* porter duff alpha mode sel */ + uint8_t PD_mode; /* porter duff alpha mode sel */ - uint8_t alpha_global_value; /* global alpha value */ + uint8_t alpha_global_value; /* global alpha value */ - uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ + uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ - uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ + uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ - uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ + uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ - uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ + uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ - uint8_t endian_mode; /* 0/big endian 1/little endian*/ + uint8_t endian_mode; /* 0/big endian 1/little endian*/ - uint8_t rotate_mode; /* (enum) rotate mode */ - /* 0x0, no rotate */ - /* 0x1, rotate */ - /* 0x2, x_mirror */ - /* 0x3, y_mirror */ + uint8_t rotate_mode; /* (enum) rotate mode */ + /* 0x0, no rotate */ + /* 0x1, rotate */ + /* 0x2, x_mirror */ + /* 0x3, y_mirror */ - uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ + uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ - MMU mmu_info; /* mmu information */ + MMU mmu_info; /* mmu information */ - uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ - /* ([2~3] rop mode) */ - /* ([4] zero mode en) */ - /* ([5] dst alpha mode) */ + uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ + /* ([2~3] rop mode) */ + /* ([4] zero mode en) */ + /* ([5] dst alpha mode) */ uint8_t src_trans_mode; @@ -388,33 +383,6 @@ typedef struct rga_service_info { -struct rga_drvdata { - struct miscdevice miscdev; - struct device dev; - void *rga_base; - int irq0; - - struct clk *pd_display; - struct clk *aclk_lcdc; - struct clk *hclk_lcdc; - struct clk *aclk_ddr_lcdc; - struct clk *hclk_cpu_display; - struct clk *aclk_disp_matrix; - struct clk *hclk_disp_matrix; - struct clk *axi_clk; - struct clk *ahb_clk; - - struct mutex mutex; // mutex - - struct delayed_work power_off_work; - bool enable; //clk enable or disable - void (*rga_irq_callback)(int rga_retval); //callback function used by aync call -}; - - - - - #define RGA_BASE 0x10114000 //General Registers diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c index a58bdd54f34a..755c6ece3c6f 100755 --- a/drivers/video/rockchip/rga/rga_drv.c +++ b/drivers/video/rockchip/rga/rga_drv.c @@ -58,13 +58,33 @@ #define RGA_POWER_OFF_DELAY 4*HZ /* 4s */ #define RGA_TIMEOUT_DELAY 2*HZ /* 2s */ +struct rga_drvdata { + struct miscdevice miscdev; + struct device dev; + void *rga_base; + int irq0; + + struct clk *pd_display; + struct clk *aclk_lcdc; + struct clk *hclk_lcdc; + struct clk *aclk_ddr_lcdc; + struct clk *hclk_cpu_display; + struct clk *aclk_disp_matrix; + struct clk *hclk_disp_matrix; + struct clk *axi_clk; + struct clk *ahb_clk; + + struct mutex mutex; // mutex + + struct delayed_work power_off_work; + bool enable; //clk enable or disable + void (*rga_irq_callback)(int rga_retval); //callback function used by aync call +}; + static struct rga_drvdata *drvdata = NULL; rga_service_info rga_service; -#if 1//def RGA_TEST -//uint32_t dst_buf[800*480*4]; -#endif static int rga_blit_async(rga_session *session, struct rga_req *req); -- 2.34.1