From b59dbc2886078e2525b73a5a7d8eddd909dd4b6d Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Tue, 14 Mar 2017 11:23:30 +0800 Subject: [PATCH] ARM64: dts: rk3368: add rk3368-sheep.dts for sheep board rework for rk3368-tb.dtsi and rk3368-tb-sheep.dts, intergrate them to rk3368-sheep.dts Change-Id: Ieb9198be7c80a5c8c31b0a1990bac22079548eea Signed-off-by: Jianqun Xu --- arch/arm64/boot/dts/rockchip/Makefile | 2 +- .../boot/dts/rockchip/rk3368-android.dtsi | 371 ++++++++++-------- .../{rk3368-tb.dtsi => rk3368-sheep.dts} | 234 +++-------- .../boot/dts/rockchip/rk3368-tb-sheep.dts | 126 ------ 4 files changed, 249 insertions(+), 484 deletions(-) rename arch/arm64/boot/dts/rockchip/{rk3368-tb.dtsi => rk3368-sheep.dts} (74%) delete mode 100644 arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ddf5913782e2..2ec03b77a63a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -4,7 +4,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3366-tb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-tb-sheep.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-sheep.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-808-android-6.0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1-android-6.0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-box-rev1-disvr.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi index b2abf8b08e31..3e25c908a79b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi @@ -137,7 +137,7 @@ status = "disabled"; }; - rga: rga@ff920000 { + rga@ff920000 { compatible = "rockchip,rga2"; dev_mode = <1>; reg = <0x0 0xff920000 0x0 0x1000>; @@ -147,15 +147,20 @@ status = "disabled"; }; - fb: fb { + fb { compatible = "rockchip,rk-fb"; + status = "okay"; + rockchip,disp-mode = ; - status = "disabled"; + rockchip,uboot-logo-on = <0>; + }; - rk_screen: screen { + screen { compatible = "rockchip,screen"; - status = "disabled"; + status = "okay"; + + #include }; lcdc: lcdc@ff930000 { @@ -175,7 +180,6 @@ /*power-domains = <&power PD_VIO>;*/ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; - status = "disabled"; }; mipi: mipi@ff960000 { @@ -187,7 +191,6 @@ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>; clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host"; /*power-domains = <&power PD_VIO>;*/ - status = "disabled"; }; lvds: lvds@ff968000 { @@ -228,77 +231,72 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>; pinctrl-1 = <&i2c5_gpio>; - status = "disabled"; + status = "okay"; }; - iep_mmu: iep-mmu { + iep-mmu { dbgname = "iep"; compatible = "rockchip,iep_mmu"; reg = <0x0 0xff900800 0x0 0x100>; interrupts = ; interrupt-names = "iep_mmu"; - status = "disabled"; }; - vip_mmu: vip-mmu { + vip-mmu { dbgname = "vip"; compatible = "rockchip,vip_mmu"; reg = <0x0 0xff950800 0x0 0x100>; interrupts = ; interrupt-names = "vip_mmu"; - status = "disabled"; }; - vopb_mmu: vopb-mmu { + vopb-mmu { dbgname = "vop"; compatible = "rockchip,vopb_mmu"; reg = <0x0 0xff930300 0x0 0x100>; interrupts = ; interrupt-names = "vop_mmu"; - status = "disabled"; }; - isp_mmu: isp-mmu { + isp-mmu { dbgname = "isp_mmu"; compatible = "rockchip,isp_mmu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; interrupts = ; interrupt-names = "isp_mmu"; - status = "disabled"; }; - hdcp_mmu: hdcp-mmu { - dbgname = "hdcp_mmu"; - compatible = "rockchip,hdcp_mmu"; - reg = <0x0 0xff940000 0x0 0x100>; - interrupts = ; - interrupt-names = "hdcp_mmu"; - status = "disabled"; + hdcp-mmu { + dbgname = "hdcp_mmu"; + compatible = "rockchip,hdcp_mmu"; + reg = <0x0 0xff940000 0x0 0x100>; + interrupts = ; + interrupt-names = "hdcp_mmu"; }; - hevc_mmu: hevc-mmu { + hevc-mmu { dbgname = "hevc"; compatible = "rockchip,hevc_mmu"; reg = <0x0 0xff9a0440 0x0 0x40>, <0x0 0xff9a0480 0x0 0x40>; interrupts = ; interrupt-names = "hevc_mmu"; - status = "disabled"; }; - vpu_mmu: vpu-mmu { + vpu-mmu { dbgname = "vpu"; compatible = "rockchip,vpu_mmu"; reg = <0x0 0xff9a0800 0x0 0x100>; interrupts = , ; interrupt-names = "vepu_mmu", "vdpu_mmu"; - status = "disabled"; }; dwc_control_usb: dwc-control-usb { compatible = "rockchip,rk3368-dwc-control-usb"; + status = "okay"; + rockchip,grf = <&grf>; grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */ interrupts = , @@ -309,7 +307,10 @@ "otg_linestate", "host0_linestate"; clocks = <&cru HCLK_USB_PERI>; clock-names = "hclk_usb_peri"; - status = "disabled"; + + otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; + rockchip,remote_wakeup; + rockchip,usb_irq_wakeup; usb_bc { compatible = "inno,phy"; @@ -327,159 +328,187 @@ rk_usb,dcpattach = <0x4b8 29 1>; }; }; +}; + +&usb_otg { + clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>; + clock-names = "sclk_otgphy0", "otg"; + resets = <&cru SRST_USBOTG_AHB>, + <&cru SRST_USBOTG_PHY>, + <&cru SRST_USBOTG_CON>; + reset-names = "otg_ahb", "otg_phy", "otg_controller"; + /* 0 - Normal, 1 - Force Host, 2 - Force Device */ + rockchip,usb-mode = <0>; +}; + +&lcdc { + status = "okay"; + backlight = <&backlight>; + rockchip,mirror = ; + rockchip,cabc_mode = <0>; + rockchip,fb-win-map = ; + power_ctr: power_ctr { + rockchip,debug = <0>; + lcd_en: lcd-en { + rockchip,power_type = ; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;/*GPIO_C6 = 22*/ + rockchip,delay = <120>; + }; + + lcd_cs: lcd-cs { + rockchip,power_type = ; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;/*GPIO_C5 = 21*/ + rockchip,delay = <10>; + }; + + /*lcd_rst: lcd-rst { + rockchip,power_type = ; + gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; + rockchip,delay = <5>; + };*/ + }; +}; - pinctrl { - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>, - <3 27 RK_FUNC_1 &pcfg_pull_none>; - }; +&pinctrl { + hdmi_i2c { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>; }; + }; - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>; - }; + hdmi_pin { + hdmi_cec: hdmi-cec { + rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>; }; + }; - i2c5 { - i2c5_gpio: i2c5-gpio { - rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>, - <3 27 RK_FUNC_GPIO &pcfg_pull_none>; - }; + i2c5 { + i2c5_gpio: i2c5-gpio { + rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>, + <3 27 RK_FUNC_GPIO &pcfg_pull_none>; }; + }; - lcdc { - lcdc_lcdc: lcdc-lcdc { - rockchip,pins = - <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10 - <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11 - <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12 - <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13 - <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14 - <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15 - <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16 - <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17 - <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18 - <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19 - <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20 - <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21 - <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22 - <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23 - <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK - <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN - <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC - <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN - }; - - lcdc_gpio: lcdc-gpio { - rockchip,pins = - <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10 - <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11 - <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12 - <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13 - <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14 - <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15 - <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16 - <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17 - <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18 - <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19 - <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20 - <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21 - <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22 - <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23 - <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK - <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN - <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC - <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN - }; + lcdc { + lcdc_lcdc: lcdc-lcdc { + rockchip,pins = + <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10 + <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11 + <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12 + <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13 + <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14 + <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15 + <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16 + <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17 + <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18 + <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19 + <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20 + <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21 + <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22 + <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23 + <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK + <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN + <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC + <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN }; - isp { - cif_clkout: cif-clkout { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout - }; - - isp_dvp_d2d9: isp-dvp-d2d9 { - rockchip,pins = - <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 - <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 - <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 - <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 - <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 - <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 - <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 - <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 - <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync - <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href - <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin - <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout - }; - - isp_dvp_d0d1: isp-dvp-d0d1 { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 - <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1 - }; - - isp_dvp_d10d11:isp_d10d11 { - rockchip,pins = - <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 - <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 - }; - - isp_dvp_d0d7: isp-dvp-d0d7 { - rockchip,pins = - <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 - <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1 - <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 - <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 - <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 - <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 - <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 - <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7 - }; - - isp_dvp_d4d11: isp-dvp-d4d11 { - rockchip,pins = - <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 - <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 - <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 - <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 - <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 - <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 - <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 - <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 - }; - - isp_shutter: isp-shutter { - rockchip,pins = - <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN - <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG - }; - - isp_flash_trigger: isp-flash-trigger { - rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU - }; - - isp_prelight: isp-prelight { - rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG - }; - - isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio { - rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU - }; + lcdc_gpio: lcdc-gpio { + rockchip,pins = + <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10 + <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11 + <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12 + <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13 + <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14 + <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15 + <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16 + <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17 + <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18 + <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19 + <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20 + <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21 + <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22 + <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23 + <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK + <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN + <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC + <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN }; }; -}; -&usb_otg { - clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>; - clock-names = "sclk_otgphy0", "otg"; - resets = <&cru SRST_USBOTG_AHB>, - <&cru SRST_USBOTG_PHY>, - <&cru SRST_USBOTG_CON>; - reset-names = "otg_ahb", "otg_phy", "otg_controller"; - /* 0 - Normal, 1 - Force Host, 2 - Force Device */ - rockchip,usb-mode = <0>; + isp { + cif_clkout: cif-clkout { + rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout + }; + + isp_dvp_d2d9: isp-dvp-d2d9 { + rockchip,pins = + <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 + <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 + <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 + <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 + <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync + <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href + <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin + <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout + }; + + isp_dvp_d0d1: isp-dvp-d0d1 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 + <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1 + }; + + isp_dvp_d10d11:isp_d10d11 { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 + <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0 + <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1 + <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2 + <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3 + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7 + }; + + isp_dvp_d4d11: isp-dvp-d4d11 { + rockchip,pins = + <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4 + <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5 + <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6 + <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7 + <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8 + <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9 + <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10 + <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11 + }; + + isp_shutter: isp-shutter { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN + <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG + }; + + isp_flash_trigger: isp-flash-trigger { + rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU + }; + + isp_prelight: isp-prelight { + rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG + }; + + isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio { + rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU + }; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts similarity index 74% rename from arch/arm64/boot/dts/rockchip/rk3368-tb.dtsi rename to arch/arm64/boot/dts/rockchip/rk3368-sheep.dts index aaf245b3d96f..de9976e0df64 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-tb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-sheep.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,12 +40,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +/dts-v1/; #include #include "rk3368.dtsi" #include "rk3368-android.dtsi" / { - compatible = "rockchip,tb", "rockchip,rk3368"; + model = "Rockchip Sheep board"; + compatible = "rockchip,sheep", "rockchip,rk3368"; sound { compatible = "simple-audio-card"; @@ -110,7 +112,7 @@ rk_key: rockchip-key { compatible = "rockchip,key"; - status = "disabled"; + status = "okay"; io-channels = <&saradc 1>; @@ -169,6 +171,7 @@ }; &emmc { + status = "okay"; bus-width = <8>; cap-mmc-highspeed; supports-emmc; @@ -177,10 +180,10 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "okay"; }; &sdmmc { + status = "okay"; clock-frequency = <37500000>; clock-freq-min-max = <400000 37500000>; supports-sd; @@ -191,7 +194,6 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; - status = "disabled"; }; &i2c0 { @@ -199,8 +201,8 @@ syr827: syr827@40 { compatible = "silergy,syr827"; - status = "disabled"; reg = <0x40>; + status = "okay"; regulator-compatible = "fan53555-reg"; regulator-name = "vdd_arm"; @@ -217,127 +219,11 @@ }; }; - syr828: syr828@41 { - compatible = "silergy,syr828"; - status = "disabled"; - reg = <0x41>; - - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_gpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1500000>; - regulator-ramp-delay = <1000>; - fcs,suspend-voltage-selector = <1>; - regulator-always-on; - regulator-boot-on; - regulator-initial-state = <3>; - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - act8846: act8846@5a { - /* - * Note: u-boot ONLY match old compatible, - * it's better to add both instances here. - */ - compatible = "act,act8846", "active-semi,act8846"; - status = "disabled"; - reg = <0x5a>; - system-power-controller; - - regulators { - act8846_reg1: REG1 { - regulator-name = "VCC_DDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - act8846_reg2: REG2 { - regulator-name = "VCC_IO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - act8846_reg3: REG3 { - regulator-name = "VDD_LOG"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - act8846_reg4: REG4 { - regulator-name = "VCC_20"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - act8846_reg5: REG5 { - regulator-name = "VCCIO_SD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - act8846_reg6: REG6 { - regulator-name = "VDD10_LCD"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - act8846_reg7: REG7 { - regulator-name = "VCCA_CODEC"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - act8846_reg8: REG8 { - regulator-name = "VCCA_TP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - act8846_reg9: REG9 { - regulator-name = "VCCIO_PMU"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - act8846_reg10: REG10 { - regulator-name = "VDD_10"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - act8846_reg11: REG11 { - regulator-name = "VCC_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - act8846_reg12: REG12 { - regulator-name = "VCC18_LCD"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - }; - rk818: pmic@1c { compatible = "rockchip,rk818"; - status = "disabled"; reg = <0x1c>; + status = "okay"; + clock-output-names = "xin32k", "wifibt_32kin"; interrupt-parent = <&gpio0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; @@ -520,34 +406,61 @@ }; }; }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; +&gpu { + logic-supply = <&vdd_logic>; }; &i2c1 { status = "okay"; rt5640: rt5640@1c { - #sound-dai-cells = <0>; compatible = "realtek,rt5640"; reg = <0x1c>; + #sound-dai-cells = <0>; clocks = <&cru SCLK_I2S_8CH_OUT>; clock-names = "mclk"; realtek,in1-differential; - status = "disabled"; + status = "okay"; }; }; &i2c2 { status = "okay"; - gt911: gt911@14 { - compatible = "goodix,gt911"; - reg = <0x14>; - interrupt-parent = <&gpio0>; - interrupts = <12 0>; - status = "disabled"; - }; - gt9xx: gt9xx@14 { compatible = "goodix,gt9xx"; reg = <0x14>; @@ -556,8 +469,8 @@ max-x = <1200>; max-y = <1900>; tp-size = <911>; - status = "disabled"; tp-supply = <&vcc_tp>; + status = "okay"; }; }; @@ -571,7 +484,6 @@ &io_domains { status = "okay"; - dvp-supply = <&vcc_18>; audio-supply = <&vcc_io>; gpio30-supply = <&vcc_io>; @@ -582,7 +494,6 @@ &pmu_io_domains { status = "okay"; - pmu-supply = <&vcc_io>; vop-supply = <&vcc_io>; }; @@ -595,47 +506,6 @@ status = "okay"; }; -&fb { - status = "okay"; - rockchip,disp-mode = ; - rockchip,uboot-logo-on = <0>; -}; - -&lcdc { - status = "okay"; - backlight = <&backlight>; - rockchip,mirror = ; - rockchip,cabc_mode = <0>; - rockchip,fb-win-map = ; - power_ctr: power_ctr { - rockchip,debug = <0>; - lcd_en: lcd-en { - rockchip,power_type = ; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;/*GPIO_C6 = 22*/ - rockchip,delay = <10>; - }; - - lcd_cs: lcd-cs { - rockchip,power_type = ; - gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;/*GPIO_C5 = 21*/ - rockchip,delay = <10>; - }; - - /*lcd_rst: lcd-rst { - rockchip,power_type = ; - gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; - rockchip,delay = <5>; - };*/ - }; -}; - -&lvds { - pinctrl-names = "lcdc", "sleep"; - pinctrl-0 = <&lcdc_lcdc>; - pinctrl-1 = <&lcdc_gpio>; - status = "disabled"; -}; - &mailbox { status = "okay"; }; @@ -644,18 +514,10 @@ status = "okay"; }; -&rga { - status = "okay"; -}; - &saradc { status = "okay"; }; -&vopb_mmu { - status = "okay"; -}; - &pinctrl { pmic { pmic_int_l: pmic-int-l { diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts deleted file mode 100644 index aa420afa11a0..000000000000 --- a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2015 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "rk3368-tb.dtsi" - -/ { - model = "Rockchip Sheep board"; - compatible = "rockchip,sheep", "rockchip,rk3368"; -}; - -&rt5640 { - status = "okay"; -}; - ->9xx { - status = "okay"; -}; - -&syr827 { - status = "okay"; -}; - -&mipi { - status = "okay"; -}; - -&rk_screen { - status = "okay"; - #include -}; - -&rk_key { - status = "okay"; -}; - -&rk818 { - status = "okay"; -}; - -&cpu_l0 { - cpu-supply = <&syr827>; -}; - -&cpu_l1 { - cpu-supply = <&syr827>; -}; - -&cpu_l2 { - cpu-supply = <&syr827>; -}; - -&cpu_l3 { - cpu-supply = <&syr827>; -}; - -&cpu_b0 { - cpu-supply = <&syr827>; -}; - -&cpu_b1 { - cpu-supply = <&syr827>; -}; - -&cpu_b2 { - cpu-supply = <&syr827>; -}; - -&cpu_b3 { - cpu-supply = <&syr827>; -}; - -&gpu { - logic-supply = <&vdd_logic>; -}; - -&dwc_control_usb { - otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; - - rockchip,remote_wakeup; - rockchip,usb_irq_wakeup; - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; -- 2.34.1