From b5b30b22f4a8507711589ba7aad341a9ff2b14bb Mon Sep 17 00:00:00 2001
From: luowei <lw@rock-chips.com>
Date: Fri, 7 Mar 2014 19:03:20 +0800
Subject: [PATCH] add spi dts code

---
 arch/arm/boot/dts/rk3188.dtsi | 38 +++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index b4834797b70b..6a6cdd5f1802 100755
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -23,6 +23,8 @@
 		i2c4 = &i2c4;
 		lcdc0 = &lcdc0;
 		lcdc1 = &lcdc1;
+		spi0 = &spi0;
+		spi1 = &spi1;
 	};
 
 	cpus {
@@ -310,6 +312,42 @@
 		status = "disabled";
 	};
 
+	spi0: spi@20070000 {
+		compatible = "rockchip,rockchip-spi";
+		reg = <0x20070000 0x500>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
+		rockchip,spi-src-clk = <0>;
+        	num-cs = <2>;
+		clocks =<&clk_spi0>, <&clk_gates7 12>;
+		clock-names = "spi","pclk_spi0";
+		dmas = <&pdma0 16>, <&pdma0 17>;
+		#dma-cells = <2>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
+	spi1: spi@20074000 {
+		compatible = "rockchip,rockchip-spi";
+		reg = <0x20074000 0x500>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
+		rockchip,spi-src-clk = <1>;
+        	num-cs = <2>;
+		clocks = <&clk_spi1>, <&clk_gates7 13>;
+		clock-names = "spi","pclk_spi1";
+		dmas = <&pdma0 16>, <&pdma0 17>;
+		#dma-cells = <2>;
+		dma-names = "tx", "rx";
+		status = "disabled";
+	};
+
 	i2c0: i2c@2002d000 {
 		compatible = "rockchip,rk30-i2c";
 		reg = <0x2002d000 0x1000>;
-- 
2.34.1