From b708944fc2752ca7f100c5a3c1f6385229777ea1 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 13 Jan 2003 00:35:03 +0000 Subject: [PATCH] * Implement rudimentary output of the constant pool * Implement support for MRMS?m instructions * Add Arg64 support * Add support for frame indexes and constant pool indexes * git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5225 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/Printer.cpp | 129 ++++++++++++++++++++++++++----- lib/Target/X86/X86AsmPrinter.cpp | 129 ++++++++++++++++++++++++++----- 2 files changed, 220 insertions(+), 38 deletions(-) diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp index 66cb15301f2..b71f3f2beb8 100644 --- a/lib/Target/X86/Printer.cpp +++ b/lib/Target/X86/Printer.cpp @@ -8,21 +8,24 @@ #include "X86.h" #include "X86InstrInfo.h" #include "llvm/Function.h" +#include "llvm/Constant.h" #include "llvm/Target/TargetMachine.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/Statistic.h" namespace { struct Printer : public MachineFunctionPass { std::ostream &O; - - Printer(std::ostream &o) : O(o) {} + unsigned ConstIdx; + Printer(std::ostream &o) : O(o), ConstIdx(0) {} virtual const char *getPassName() const { return "X86 Assembly Printer"; } + void printConstantPool(MachineConstantPool *MCP, const TargetData &TD); bool runOnMachineFunction(MachineFunction &F); }; } @@ -36,6 +39,21 @@ Pass *createX86CodePrinterPass(std::ostream &O) { } +// printConstantPool - Print out any constants which have been spilled to +// memory... +void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){ + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) return; + + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + O << "\t.section .rodata\n"; + O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n"; + O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n"; + O << "\t*Constant output not implemented yet!*\n\n"; + } + ConstIdx += CP.size(); // Don't recycle constant pool index numbers +} + /// runOnFunction - This uses the X86InstructionInfo::print method /// to print assembly for each instruction. bool Printer::runOnMachineFunction(MachineFunction &MF) { @@ -43,7 +61,12 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) { const TargetMachine &TM = MF.getTarget(); const MachineInstrInfo &MII = TM.getInstrInfo(); + // Print out constants referenced by the function + printConstantPool(MF.getConstantPool(), TM.getTargetData()); + // Print out labels for the function. + O << "\t.text\n"; + O << "\t.align 16\n"; O << "\t.globl\t" << MF.getFunction()->getName() << "\n"; O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n"; O << MF.getFunction()->getName() << ":\n"; @@ -72,6 +95,8 @@ static bool isScale(const MachineOperand &MO) { } static bool isMem(const MachineInstr *MI, unsigned Op) { + if (MI->getOperand(Op).isFrameIndex()) return true; + if (MI->getOperand(Op).isConstantPoolIndex()) return true; return Op+4 <= MI->getNumOperands() && MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); @@ -85,6 +110,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO, O << "<" << V->getName() << ">"; return; } + // FALLTHROUGH case MachineOperand::MO_MachineRegister: if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) O << RI.get(MO.getReg()).Name; @@ -99,6 +125,12 @@ static void printOp(std::ostream &O, const MachineOperand &MO, case MachineOperand::MO_PCRelativeDisp: O << "<" << MO.getVRegValue()->getName() << ">"; return; + case MachineOperand::MO_GlobalAddress: + O << "<" << MO.getGlobal()->getName() << ">"; + return; + case MachineOperand::MO_ExternalSymbol: + O << "<" << MO.getSymbolName() << ">"; + return; default: O << ""; return; } @@ -110,6 +142,7 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) { case X86II::Arg8: return "BYTE PTR"; case X86II::Arg16: return "WORD PTR"; case X86II::Arg32: return "DWORD PTR"; + case X86II::Arg64: return "QWORD PTR"; case X86II::ArgF32: return "DWORD PTR"; case X86II::ArgF64: return "QWORD PTR"; case X86II::ArgF80: return "XWORD PTR"; @@ -119,6 +152,21 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) { static void printMemReference(std::ostream &O, const MachineInstr *MI, unsigned Op, const MRegisterInfo &RI) { assert(isMem(MI, Op) && "Invalid memory reference!"); + + if (MI->getOperand(Op).isFrameIndex()) { + O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } else if (MI->getOperand(Op).isConstantPoolIndex()) { + O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } + const MachineOperand &BaseReg = MI->getOperand(Op); int ScaleVal = MI->getOperand(Op+1).getImmedValue(); const MachineOperand &IndexReg = MI->getOperand(Op+2); @@ -194,9 +242,13 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // The accepted forms of Raw instructions are: // 1. nop - No operand required // 2. jmp foo - PC relative displacement operand + // 3. call bar - GlobalAddress Operand or External Symbol Operand // assert(MI->getNumOperands() == 0 || - (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&& + (MI->getNumOperands() == 1 && + (MI->getOperand(0).isPCRelativeDisp() || + MI->getOperand(0).isGlobalAddress() || + MI->getOperand(0).isExternalSymbol())) && "Illegal raw instruction!"); O << getName(MI->getOpcode()) << " "; @@ -220,14 +272,20 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, (MI->getNumOperands() == 2 && (MI->getOperand(1).getVRegValueOrNull() || MI->getOperand(1).isImmediate() || - MI->getOperand(1).isRegister()))) && + MI->getOperand(1).isRegister() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol()))) && "Illegal form for AddRegFrm instruction!"); unsigned Reg = MI->getOperand(0).getReg(); O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) { + if (MI->getNumOperands() == 2 && + (!MI->getOperand(1).isRegister() || + MI->getOperand(1).getVRegValueOrNull() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol())) { O << ", "; printOp(O, MI->getOperand(1), RI); } @@ -235,29 +293,36 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } case X86II::MRMDestReg: { - // There are two acceptable forms of MRMDestReg instructions, those with 3 - // and 2 operands: + // There are two acceptable forms of MRMDestReg instructions, those with 2, + // 3 and 4 operands: + // + // 2 Operands: this is for things like mov that do not read a second input // // 3 Operands: in this form, the first two registers (the destination, and // the first operand) should be the same, post register allocation. The 3rd // operand is an additional input. This should be for things like add // instructions. // - // 2 Operands: this is for things like mov that do not read a second input + // 4 Operands: This form is for instructions which are 3 operands forms, but + // have a constant argument as well. // + bool isTwoAddr = isTwoAddrInstr(Opcode); assert(MI->getOperand(0).isRegister() && - (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) && - MI->getOperand(MI->getNumOperands()-1).isRegister() + (MI->getNumOperands() == 2 || + (isTwoAddr && MI->getOperand(1).isRegister() && + MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && + (MI->getNumOperands() == 3 || + (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate())))) && "Bad format for MRMDestReg!"); - if (MI->getNumOperands() == 3 && - MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) - O << "**"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); O << ", "; - printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); + printOp(O, MI->getOperand(1+isTwoAddr), RI); + if (MI->getNumOperands() == 4) { + O << ", "; + printOp(O, MI->getOperand(3), RI); + } O << "\n"; return; } @@ -269,7 +334,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); - O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " "; + O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " "; printMemReference(O, MI, 0, RI); O << ", "; printOp(O, MI->getOperand(4), RI); @@ -291,7 +356,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, MI->getOperand(1).isRegister() && (MI->getNumOperands() == 2 || (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister())) - && "Bad format for MRMDestReg!"); + && "Bad format for MRMSrcReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; @@ -319,7 +384,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - O << ", " << sizePtr (Desc) << " "; + O << ", " << sizePtr(Desc) << " "; printMemReference(O, MI, MI->getNumOperands()-4, RI); O << "\n"; return; @@ -359,7 +424,33 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } + case X86II::MRMS0m: case X86II::MRMS1m: + case X86II::MRMS2m: case X86II::MRMS3m: + case X86II::MRMS4m: case X86II::MRMS5m: + case X86II::MRMS6m: case X86II::MRMS7m: { + // In this form, the following are valid formats: + // 1. sete [m] + // 2. cmp [m], immediate + // 2. shl [m], rinput + // 3. sbb [m], immediate + // + assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && + isMem(MI, 0) && "Bad MRMSxM format!"); + assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) && + "Bad MRMSxM format!"); + + O << getName(MI->getOpCode()) << " "; + O << sizePtr(Desc) << " "; + printMemReference(O, MI, 0, RI); + if (MI->getNumOperands() == 5) { + O << ", "; + printOp(O, MI->getOperand(4), RI); + } + O << "\n"; + return; + } + default: - O << "\t\t\t-"; MI->print(O, TM); break; + O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; } } diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp index 66cb15301f2..b71f3f2beb8 100644 --- a/lib/Target/X86/X86AsmPrinter.cpp +++ b/lib/Target/X86/X86AsmPrinter.cpp @@ -8,21 +8,24 @@ #include "X86.h" #include "X86InstrInfo.h" #include "llvm/Function.h" +#include "llvm/Constant.h" #include "llvm/Target/TargetMachine.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstr.h" #include "Support/Statistic.h" namespace { struct Printer : public MachineFunctionPass { std::ostream &O; - - Printer(std::ostream &o) : O(o) {} + unsigned ConstIdx; + Printer(std::ostream &o) : O(o), ConstIdx(0) {} virtual const char *getPassName() const { return "X86 Assembly Printer"; } + void printConstantPool(MachineConstantPool *MCP, const TargetData &TD); bool runOnMachineFunction(MachineFunction &F); }; } @@ -36,6 +39,21 @@ Pass *createX86CodePrinterPass(std::ostream &O) { } +// printConstantPool - Print out any constants which have been spilled to +// memory... +void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){ + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) return; + + for (unsigned i = 0, e = CP.size(); i != e; ++i) { + O << "\t.section .rodata\n"; + O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n"; + O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n"; + O << "\t*Constant output not implemented yet!*\n\n"; + } + ConstIdx += CP.size(); // Don't recycle constant pool index numbers +} + /// runOnFunction - This uses the X86InstructionInfo::print method /// to print assembly for each instruction. bool Printer::runOnMachineFunction(MachineFunction &MF) { @@ -43,7 +61,12 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) { const TargetMachine &TM = MF.getTarget(); const MachineInstrInfo &MII = TM.getInstrInfo(); + // Print out constants referenced by the function + printConstantPool(MF.getConstantPool(), TM.getTargetData()); + // Print out labels for the function. + O << "\t.text\n"; + O << "\t.align 16\n"; O << "\t.globl\t" << MF.getFunction()->getName() << "\n"; O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n"; O << MF.getFunction()->getName() << ":\n"; @@ -72,6 +95,8 @@ static bool isScale(const MachineOperand &MO) { } static bool isMem(const MachineInstr *MI, unsigned Op) { + if (MI->getOperand(Op).isFrameIndex()) return true; + if (MI->getOperand(Op).isConstantPoolIndex()) return true; return Op+4 <= MI->getNumOperands() && MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); @@ -85,6 +110,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO, O << "<" << V->getName() << ">"; return; } + // FALLTHROUGH case MachineOperand::MO_MachineRegister: if (MO.getReg() < MRegisterInfo::FirstVirtualRegister) O << RI.get(MO.getReg()).Name; @@ -99,6 +125,12 @@ static void printOp(std::ostream &O, const MachineOperand &MO, case MachineOperand::MO_PCRelativeDisp: O << "<" << MO.getVRegValue()->getName() << ">"; return; + case MachineOperand::MO_GlobalAddress: + O << "<" << MO.getGlobal()->getName() << ">"; + return; + case MachineOperand::MO_ExternalSymbol: + O << "<" << MO.getSymbolName() << ">"; + return; default: O << ""; return; } @@ -110,6 +142,7 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) { case X86II::Arg8: return "BYTE PTR"; case X86II::Arg16: return "WORD PTR"; case X86II::Arg32: return "DWORD PTR"; + case X86II::Arg64: return "QWORD PTR"; case X86II::ArgF32: return "DWORD PTR"; case X86II::ArgF64: return "QWORD PTR"; case X86II::ArgF80: return "XWORD PTR"; @@ -119,6 +152,21 @@ static const std::string sizePtr(const MachineInstrDescriptor &Desc) { static void printMemReference(std::ostream &O, const MachineInstr *MI, unsigned Op, const MRegisterInfo &RI) { assert(isMem(MI, Op) && "Invalid memory reference!"); + + if (MI->getOperand(Op).isFrameIndex()) { + O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } else if (MI->getOperand(Op).isConstantPoolIndex()) { + O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex(); + if (MI->getOperand(Op+3).getImmedValue()) + O << " + " << MI->getOperand(Op+3).getImmedValue(); + O << "]"; + return; + } + const MachineOperand &BaseReg = MI->getOperand(Op); int ScaleVal = MI->getOperand(Op+1).getImmedValue(); const MachineOperand &IndexReg = MI->getOperand(Op+2); @@ -194,9 +242,13 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, // The accepted forms of Raw instructions are: // 1. nop - No operand required // 2. jmp foo - PC relative displacement operand + // 3. call bar - GlobalAddress Operand or External Symbol Operand // assert(MI->getNumOperands() == 0 || - (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&& + (MI->getNumOperands() == 1 && + (MI->getOperand(0).isPCRelativeDisp() || + MI->getOperand(0).isGlobalAddress() || + MI->getOperand(0).isExternalSymbol())) && "Illegal raw instruction!"); O << getName(MI->getOpcode()) << " "; @@ -220,14 +272,20 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, (MI->getNumOperands() == 2 && (MI->getOperand(1).getVRegValueOrNull() || MI->getOperand(1).isImmediate() || - MI->getOperand(1).isRegister()))) && + MI->getOperand(1).isRegister() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol()))) && "Illegal form for AddRegFrm instruction!"); unsigned Reg = MI->getOperand(0).getReg(); O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - if (MI->getNumOperands() == 2 && !MI->getOperand(1).isRegister()) { + if (MI->getNumOperands() == 2 && + (!MI->getOperand(1).isRegister() || + MI->getOperand(1).getVRegValueOrNull() || + MI->getOperand(1).isGlobalAddress() || + MI->getOperand(1).isExternalSymbol())) { O << ", "; printOp(O, MI->getOperand(1), RI); } @@ -235,29 +293,36 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } case X86II::MRMDestReg: { - // There are two acceptable forms of MRMDestReg instructions, those with 3 - // and 2 operands: + // There are two acceptable forms of MRMDestReg instructions, those with 2, + // 3 and 4 operands: + // + // 2 Operands: this is for things like mov that do not read a second input // // 3 Operands: in this form, the first two registers (the destination, and // the first operand) should be the same, post register allocation. The 3rd // operand is an additional input. This should be for things like add // instructions. // - // 2 Operands: this is for things like mov that do not read a second input + // 4 Operands: This form is for instructions which are 3 operands forms, but + // have a constant argument as well. // + bool isTwoAddr = isTwoAddrInstr(Opcode); assert(MI->getOperand(0).isRegister() && - (MI->getNumOperands() == 2 || - (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) && - MI->getOperand(MI->getNumOperands()-1).isRegister() + (MI->getNumOperands() == 2 || + (isTwoAddr && MI->getOperand(1).isRegister() && + MI->getOperand(0).getReg() == MI->getOperand(1).getReg() && + (MI->getNumOperands() == 3 || + (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate())))) && "Bad format for MRMDestReg!"); - if (MI->getNumOperands() == 3 && - MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) - O << "**"; O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); O << ", "; - printOp(O, MI->getOperand(MI->getNumOperands()-1), RI); + printOp(O, MI->getOperand(1+isTwoAddr), RI); + if (MI->getNumOperands() == 4) { + O << ", "; + printOp(O, MI->getOperand(3), RI); + } O << "\n"; return; } @@ -269,7 +334,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 && MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!"); - O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " "; + O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " "; printMemReference(O, MI, 0, RI); O << ", "; printOp(O, MI->getOperand(4), RI); @@ -291,7 +356,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, MI->getOperand(1).isRegister() && (MI->getNumOperands() == 2 || (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister())) - && "Bad format for MRMDestReg!"); + && "Bad format for MRMSrcReg!"); if (MI->getNumOperands() == 3 && MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) O << "**"; @@ -319,7 +384,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, O << getName(MI->getOpCode()) << " "; printOp(O, MI->getOperand(0), RI); - O << ", " << sizePtr (Desc) << " "; + O << ", " << sizePtr(Desc) << " "; printMemReference(O, MI, MI->getNumOperands()-4, RI); O << "\n"; return; @@ -359,7 +424,33 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O, return; } + case X86II::MRMS0m: case X86II::MRMS1m: + case X86II::MRMS2m: case X86II::MRMS3m: + case X86II::MRMS4m: case X86II::MRMS5m: + case X86II::MRMS6m: case X86II::MRMS7m: { + // In this form, the following are valid formats: + // 1. sete [m] + // 2. cmp [m], immediate + // 2. shl [m], rinput + // 3. sbb [m], immediate + // + assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && + isMem(MI, 0) && "Bad MRMSxM format!"); + assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) && + "Bad MRMSxM format!"); + + O << getName(MI->getOpCode()) << " "; + O << sizePtr(Desc) << " "; + printMemReference(O, MI, 0, RI); + if (MI->getNumOperands() == 5) { + O << ", "; + printOp(O, MI->getOperand(4), RI); + } + O << "\n"; + return; + } + default: - O << "\t\t\t-"; MI->print(O, TM); break; + O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; } } -- 2.34.1